參數(shù)資料
型號(hào)： MSC8144EC
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類： 數(shù)字信號(hào)處理
英文描述： Quad Core Digital Signal Processor
中文描述： 四核心數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 57/80頁(yè)
文件大小： 1145K
代理商： MSC8144EC
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor
57
Figure 31. SMII Mode Signal Timing
2.7.10.6
RGMII AC Timing Specifications
Table 50
presents the RGMII AC timing specifications for applications requiring an on-board delayed clock.
Table 51
presents the RGMII AC timing specification for applications required non-delayed clock on board.
Table 50. RGMII with On-Board Delay AC Timing Specifications
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Data to clock output skew (at transmitter)
Data to clock input skew (at receiver)
2
Clock cycle duration
3
Duty cycle for 1000Base-T
4, 5
Duty cycle for 10BASE-T and 100BASE-TX
3, 5
Rise time (20%–80%)
Fall time (20%–80%)
GTX_CLK125 reference clock period
GTX_CLK125 reference clock duty cycle
Notes:
1.
At recommended operating conditions with LV
DD
of 2.5 V +/- 5%.
2.
This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns will
be added to the associated clock signal.
3.
For 10 and 100 Mbps, t
RGT
scales to 400 ns +/- 40 ns and 40 ns +/- 4 ns, respectively.
4.
Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long
as the minimum duty cycle is not violated and stretching occurs for no more than three t
RGT
of the lowest speed transitioned
between.
5.
Duty cycle reference is L
Vdd
/2.
6.
This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.
7.
GCR4 should be programmed as 0x00001004.
t
SKEWT
t
SKEWR
t
RGT
t
RGTH
/t
RGT
t
RGTH
/t
RGT
t
RGTR
t
RGTF
t
G12
6
t
G125H
/t
G125
-0.5
0.9
7.2
45
40
—
—
—
47
—
—
8.0
50
50
—
—
8.0
—
0.5
2.6
8.8
55
60
0.75
0.75
—
53
ns
ns
ns
%
%
ns
ns
ns
%
Table 51. RGMII with No On-Board Delay AC Timing Specifications
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Data to clock output skew (at transmitter)
Data to clock input skew (at receiver)
2
Clock cycle duration
3
Duty cycle for 1000Base-T
4, 5
Duty cycle for 10BASE-T and 100BASE-TX
3, 5
t
SKEWT
t
SKEWR
t
RGT
t
RGTH
/t
RGT
t
RGTH
/t
RGT
t
RGTR
t
RGTF
t
G12
6
–2.6
—
–0.9
ns
–0.5
—
0.5
ns
7.2
8.0
8.8
ns
45
50
55
%
40
50
60
%
Rise time (20%–80%)
—
—
0.75
ns
Fall time (20%–80%)
—
—
0.75
ns
GTX_CLK125 reference clock period
—
8.0
—
ns
Valid
ETHCLOCK
ETHSYNC_IN
ETHRXD
ETHSYNC
ETHTXD
Valid
Valid
t
SMXR
t
SMDXKH
t
SMDVKH
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