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參數(shù)資料
| 型號： | MSC8144EC |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Quad Core Digital Signal Processor |
| 中文描述： | 四核心數(shù)字信號處理器 |
| 文件頁數(shù)： | 36/80頁 |
| 文件大?。?/td> | 1145K |
| 代理商： | MSC8144EC |
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MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor
36
2.7.3
Reset Timing
The MSC8144EC has several inputs to the reset logic:
Power-on reset (
PORESET
)
External hard reset (
HRESET
)
External soft reset (
SRESET
)
Software watchdog reset
JTAG reset
RapidIO reset
Software hard reset
Software soft reset
All MSC8144EC reset sources are fed into the reset controller, which takes different actions depending on the source of the
reset. The reset status register indicates the most recent sources to cause a reset.
Table 22
describes the reset sources.
Table 22. Reset Sources
Table 21. Clock Parameters
Characteristic
Min
Max
Unit
CLKIN slew rate (20%-80%)
1
—
V/ns
PCI_CLK_IN slew rate (20%-80%)
1
—
V/ns
Name
Direction
Description
Power-on reset
(PORESET)
Input
Initiates the power-on reset flow that resets the MSC8144EC and configures various attributes of the
MSC8144EC. On PORESET, the entire MSC8144EC device is reset. All PLLs states is reset,
HRESET and SRESET are driven, the extended cores are reset, and system configuration is
sampled. The reset source and word are configured only when PORESET is asserted.
External hard
reset (HRESET)
Input/ Output
Initiates the hard reset flow that configures various attributes of the MSC8144EC. While HRESET is
asserted, SRESET is also asserted. HRESET is an open-drain pin. Upon hard reset, HRESET and
SRESET are driven, the extended cores are reset, and system configuration is sampled. Note that
the RCW (reset Configuration Word) is not reloaded during HRESET assertion after out of power on
reset sequence. The reset configuration word is described in the Reset chapter in the MSC8144EC
Reference Manual.
External soft reset
(SRESET)
Input/ Output
Initiates the soft reset flow. The MSC8144EC detects an external assertion of SRESET only if it
occurs while the MSC8144EC is not asserting reset. SRESET is an open-drain pin. Upon soft reset,
SRESET is driven, the extended cores are reset, and system configuration is maintained.
Host reset
command through
the TAP
Internal
When a host reset command is written through the Test Access Port (TAP), the TAP logic asserts the
soft reset signal and an internal soft reset sequence is generated.
Software
watchdog reset
Internal
When the MSC8144EC watchdog count reaches zero, a software watchdog reset is signalled. The
enabled software watchdog event then generates an internal hard reset sequence.
RapidIO reset
Internal
When the RapidIO logic asserts the RapidIO hard reset signal, it generates an internal hard reset
sequence.
Software hard
reset
Internal
A hard reset sequence can be initialized by writing to a memory mapped register (RCR)
Software soft reset
Internal
A soft reset sequence can be initialized by writing to a memory mapped register (RCR)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSC8144ESVT1000B | 制造商:Freescale Semiconductor 功能描述:DSP 32-BIT 1GHZ 1000MIPS 783-PIN FCBGA BOX - Trays 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA |
| MSC8144ESVT800A | 制造商:Freescale Semiconductor 功能描述:DSP 32BIT 800MHZ 800MIPS 783FCBGA - Trays |
| MSC8144ESVT800B | 制造商:Freescale Semiconductor 功能描述:DSP 32-BIT 800MHZ 800MIPS 783-PIN FCBGA EACH - Bulk 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA |
| MSC8144ETVT1000A | 制造商:Freescale Semiconductor 功能描述:DSP 32-BIT 1GHZ 1000MIPS 783-PIN FCBGA - Bulk |
| MSC8144ETVT1000B | 制造商:Freescale Semiconductor 功能描述:DSP 32-BIT 1GHZ 1000MIPS 783-PIN FCBGA EACH - Bulk 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA |
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