參數(shù)資料
型號: MSC8144EC
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類: 數(shù)字信號處理
英文描述: Quad Core Digital Signal Processor
中文描述: 四核心數(shù)字信號處理器
文件頁數(shù): 44/80頁
文件大?。?/td> 1145K
代理商: MSC8144EC
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor
44
For each baud rate at which an LP-Serial transmitter is specified to operate, the output eye pattern of the transmitter shall fall
entirely within the unshaded portion of the transmitter output compliance mask shown in
Figure 13
with the parameters
specified in
Table 36
when measured at the output pins of the device and the device is driving a 100
Ω
±
5% differential resistive
load. The output eye pattern of an LP-Serial transmitter that implements pre-emphasis (to equalize the link and reduce
inter-symbol interference) need only comply with the transmitter output compliance mask when pre-emphasis is disabled or
minimized.
Table 33. Long Run Transmitter AC Timing Specifications—1.25 GBaud
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Output Voltage,
V
O
-0.40
2.30
V
Voltage relative to COMMON of either signal
comprising a differential pair
Differential Output Voltage
V
DIFFPP
J
D
J
T
S
MO
800
1600
mV
PP
UI
PP
UI
PP
ps
Deterministic Jitter
0.17
Total Jitter
0.35
Multiple output skew
1000
Skew at the transmitter output between lanes of a
multilane link
Unit Interval
UI
800
800
ps
±
100 ppm
Table 34. Long Run Transmitter AC Timing Specifications—2.5 GBaud
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Output Voltage,
V
O
-0.40
2.30
V
Voltage relative to COMMON of either signal
comprising a differential pair
Differential Output Voltage
V
DIFFPP
J
D
J
T
S
MO
800
1600
mV
PP
UI
PP
UI
PP
ps
Deterministic Jitter
0.17
Total Jitter
0.35
Multiple output skew
1000
Skew at the transmitter output between lanes of a
multilane link
Unit Interval
UI
400
400
ps
±
100 ppm
Table 35. Long Run Transmitter AC Timing Specifications—3.125 GBaud
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Output Voltage,
V
O
-0.40
2.30
V
Voltage relative to COMMON of either signal
comprising a differential pair
Differential Output Voltage
V
DIFFPP
J
D
J
T
S
MO
800
1600
mV
PP
UI
PP
UI
PP
ps
Deterministic Jitter
0.17
Total Jitter
0.35
Multiple output skew
1000
Skew at the transmitter output between lanes of a
multilane link
Unit Interval
UI
320
320
ps
±
100 ppm
相關(guān)PDF資料
PDF描述
MSC8144E Quad Core Digital Signal Processor
MSC8144 Quad Core Digital Signal Processor
MSC82005 RF & MICROWAVE TRANSISTORS GENERAL PURPOSE AMPLIFIER APPLICATIONS
MSC82010 RF & MICROWAVE TRANSISTORS GENERAL PURPOSE AMPLIFIER APPLICATIONS
MSC82040 RF & MICROWAVE TRANSISTORS GENERAL PURPOSE LINEAR APPLICATIONS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MSC8144ESVT1000B 制造商:Freescale Semiconductor 功能描述:DSP 32-BIT 1GHZ 1000MIPS 783-PIN FCBGA BOX - Trays 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA
MSC8144ESVT800A 制造商:Freescale Semiconductor 功能描述:DSP 32BIT 800MHZ 800MIPS 783FCBGA - Trays
MSC8144ESVT800B 制造商:Freescale Semiconductor 功能描述:DSP 32-BIT 800MHZ 800MIPS 783-PIN FCBGA EACH - Bulk 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA
MSC8144ETVT1000A 制造商:Freescale Semiconductor 功能描述:DSP 32-BIT 1GHZ 1000MIPS 783-PIN FCBGA - Bulk
MSC8144ETVT1000B 制造商:Freescale Semiconductor 功能描述:DSP 32-BIT 1GHZ 1000MIPS 783-PIN FCBGA EACH - Bulk 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA