參數(shù)資料
型號(hào)： MSC8144EC
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類： 數(shù)字信號(hào)處理
英文描述： Quad Core Digital Signal Processor
中文描述： 四核心數(shù)字信號(hào)處理器
文件頁數(shù)： 39/80頁
文件大?。?/td> 1145K
代理商： MSC8144EC
Electrical Characteristics
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor
39
Table 26
provides the input AC timing specifications for the DDR SDRAM when
V
DDDDR
(typ) = 1.8 V.
Table 27
provides the input AC timing specifications for the DDR SDRAM interface.
2.7.4.2
DDR SDRAM Output AC Timing Specifications
Table 28
provides the output AC timing specifications for the DDR SDRAM interface.
AC input high voltage
V
IH
MV
REF
+ 0.31
—
V
Note:
At recommended operating conditions with V
DDDDR
of 2.5
±
5%.
Table 26. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
Parameter
Symbol
Min
Max
Unit
AC input low voltage
V
IL
—
MV
REF
– 0.25
V
AC input high voltage
V
IH
MV
REF
+ 0.25
—
V
Note:
At recommended operating conditions with V
DDDDR
of 1.8
±
5%.
Table 27. DDR SDRAM Input AC Timing Specifications
Parameter
Symbol
Min
Max
Unit
Controller Skew for MDQS—MDQ/MECC/MDM
1
400 MHz
333 MHz
266 MHz
200 MHz
Notes:
1.
t
CISKEW
represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is
captured with MDQS[n]. Subtract this value from the total timing budget.
2.
At recommended operating conditions with V
DDDDR
(1.8 V or 2.5 V)
±
5%
t
CISKEW
–365
–390
–428
–490
365
390
428
490
ps
ps
ps
ps
Table 28. DDR SDRAM Output AC Timing Specifications
Parameter
Symbol
1
Min
Max
Unit
MCK[n] cycle time, (MCK[n]/MCK[n] crossing)
2
ADDR/CMD output setup with respect to MCK
3
400 MHz
333 MHz
266 MHz
200 MHz
ADDR/CMD output hold with respect to MCK
3
400 MHz
333 MHz
266 MHz
200 MHz
MCSn output setup with respect to MCK
3
400 MHz
333 MHz
266 MHz
200 MHz
MCSn output hold with respect to MCK
3
400 MHz
333 MHz
266 MHz
200 MHz
MCK to MDQS Skew
4
t
MCK
t
DDKHAS
3
10
ns
1.95
2.40
3.15
4.20
—
—
—
—
ns
ns
ns
ns
t
DDKHAX
1.95
2.40
3.15
4.20
—
—
—
—
ns
ns
ns
ns
t
DDKHCS
1.95
2.40
3.15
4.20
—
—
—
—
ns
ns
ns
ns
t
DDKHCX
1.95
2.40
3.15
4.20
–0.6
—
—
—
—
0.6
ns
ns
ns
ns
ns
t
DDKHMH
Table 25. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface (continued)
Parameter
Symbol
Min
Max
Unit
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