參數(shù)資料
型號(hào)： MSC8144
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類： 數(shù)字信號(hào)處理
英文描述： Quad Core Digital Signal Processor
中文描述： 四核心數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 66/80頁(yè)
文件大?。?/td> 1146K
代理商： MSC8144
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1
Hardware Design Considerations
Freescale Semiconductor
66
3.1.2
Start-Up Timing
Section 2.7.1
describes the start-up timing.
3.2
Power Supply Design Considerations
3.2.1
PLL Supplies
Each PLL supply must have an external RC filter for the
V
DDPLL
input. The filter is a 10
Ω
resistor in series with two 2.2
μ
F,
low ESL (<0.5 nH) and low ESR capacitors. All three PLLs can connect to a single supply voltage source (such as a voltage
regulator) as long as the external RC filter is applied to each PLL separately (see
Figure 46
). For optimal noise filtering, place
the circuit as close as possible to its
V
DDPLL
inputs. These traces should be short and direct.
Figure 46. PLL Supplies
3.2.2
Other Supplies
TBD
3.3
Connectivity Guidelines
Note:
Although the package actually uses a ball grid array, the more conventional term pin is used to denote signal
connections in this discussion.
First, select the pin multiplexing mode to allocate the required I/O signals. Then use the guidelines presented in the following
subsections for board design and connections. The following conventions are used in describing the connectivity requirements:
1.
GND indicates using a 10 k
Ω
pull-down resistor (recommended) or a direct connection to the ground plane. Direct
connections to the ground plane may yield DC current up to 50mA through the I/O supply that adds to overall power
consumption.
MSC8144
V
DDPLL0
10
Ω
2.2
μ
F
2.2
μ
F
V
DDPLL0
10
Ω
2.2
μ
F
2.2
μ
F
V
DDPLL0
10
Ω
2.2
μ
F
2.2
μ
F
Voltage Regulator
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