參數(shù)資料
型號(hào)： MSC8144
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類： 數(shù)字信號(hào)處理
英文描述： Quad Core Digital Signal Processor
中文描述： 四核心數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 65/80頁(yè)
文件大小： 1146K
代理商： MSC8144
Hardware Design Considerations
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1
Freescale Semiconductor
65
3
Hardware Design Considerations
The following sections discuss areas to consider when the MSC8144 device is designed into a system.
3.1
Start-up Sequencing Recommendations
3.1.1
Power-on Sequence
Use the following guidelines for power-on sequencing:
There are no dependencies in power-on/power-off sequence between V
DDM3
and V
DD
supplies.
There are no dependencies in power-on/power-off sequence between RapidIO supplies: V
DDSXC
, V
DDSXP
,
V
DDRIOPLL
and other MSC8144 supplies.
V
DDPLL
should be coupled with the V
DD
power rail with extremely low impedance path.
External voltage applied to any input line must not exceed the related to this port I/O supply by more than 0.6 V at any time,
including during power-up. Some designs require pull-up voltages applied to selected input lines during power-up for
configuration purposes. This is an acceptable exception to the rule during start-up. However, each such input can draw up to 80
mA per input pin per MSC8144 device in the system during start-up. An assertion of the inputs to the high voltage level before
power-up should be with slew rate less than 4V/ns.
The following supplies should rise before any other supplies in any sequence
V
DD
and V
DDPLL
coupled together
V
DDM3
After
t
he above supplies rise to 90% of their nominal value the following I/O supplies may rise in any sequence (see
Figure 45
):
V
DDGE1
V
DDGE2
V
DDIO
V
DDDDR
and M
V
REF
coupled one to another. M
V
REF
should be either at same time or after
V
DDDDR
.
V
DDM3IO
V
25M3
Note:
1.
2.
3.
4.
5.
6.
This recommended power sequencing is different from the MSC8122/MSC8126.
If no pins that require V
DDGE1
as a reference supply are used (see
Table 1
), V
DDGE1
can be tied to GND.
If no pins that require V
DDGE2
as a reference supply are used (see
Table 1
), V
DDGE2
can be tied to GND.
If the DDR interface is not used, V
DDDDR
and MV
REF
can be tied to GND.
If the M3 memory is not used, V
DDM3
, V
DDM3IO
, and V
25M3
can be tied to GND.
If the RapidIO interface is not used, V
DDSX
, V
DDSXP
, and V
DDRIOPLL
can be tied to GND.
Figure 45. V
DDM3
, V
DDM3IO
and V
25M3
Power-on Sequenc
e
V
DDM3,
V
DD,
and V
DDPLL
90%
I/O supplies
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