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參數(shù)資料
| 型號(hào)： | MSC8144 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Quad Core Digital Signal Processor |
| 中文描述： | 四核心數(shù)字信號(hào)處理器 |
| 文件頁數(shù)： | 61/80頁 |
| 文件大?。?/td> | 1146K |
| 代理商： | MSC8144 |
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MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1
Freescale Semiconductor
61
2.7.12
SPI Timing
Table 49
provides the SPI input and output AC timing specifications.
Figure 36
provides the AC test load for the SPI.
Figure 36. SPI AC Test Load
Figure 37
through
Figure 38
represent the AC timings from
Table 49
. Note that although the specifications generally reference
the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge.
Figure 37
shows the SPI timings in slave mode (external clock).
Figure 37. SPI AC Timing in Slave Mode (External Clock)
Figure 38
shows the SPI timings in master mode (internal clock).
Table 50. SPI AC Timing Specifications
1
Characteristic
Symbol
2
Min
Max
Unit
SPI outputs valid—Master mode (internal clock) delay
t
NIKHOV
6
ns
SPI outputs hold—Master mode (internal clock) delay
t
NIKHOX
0.5
ns
SPI outputs valid—Slave mode (external clock) delay
t
NEKHOV
8
ns
SPI outputs hold—Slave mode (external clock) delay
t
NEKHOX
2
ns
SPI inputs—Master mode (internal clock input setup time
t
NIIVKH
4
ns
SPI inputs—Master mode (internal clock input hold time
t
NIIXKH
0
ns
SPI inputs—Slave mode (external clock) input setup time
t
NEIVKH
4
ns
SPI inputs—Slave mode (external clock) input hold time
t
NEIXKH
2
ns
Notes:
1. Output specifications are measured from the 50 percent level of the rising edge of CLKIN to the 50 percent level of the signal.
Timings are measured at the pin.
2. The symbols for timing specifications follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs
and t
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
NIKHOX
symbolizes the internal timing
(NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).
Output
Z
0
= 50
Ω
OV
DD
/2
R
L
= 50
Ω
SPICLK (Input)
t
NEIXKH
t
NEIVKH
t
NEKHOX
Input Signals:
SPIMOSI
(See Note)
Output Signals:
SPIMISO
(See Note)
Note:
The clock edge is selectable on SPI.
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