參數(shù)資料
型號(hào)： MSC8144
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類： 數(shù)字信號(hào)處理
英文描述： Quad Core Digital Signal Processor
中文描述： 四核心數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 39/80頁(yè)
文件大?。?/td> 1146K
代理商： MSC8144
Electrical Characteristics
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1
Freescale Semiconductor
39
See also Reset Errata for PLL lock and reset duration.
2.7.4
DDR SDRAM AC Timing Specifications
This section describes the AC electrical characteristics for the DDR SDRAM interface.
2.7.4.1
DDR SDRAM Input Timings
Table 22
provides the input AC timing specifications for the DDR SDRAM when
V
DD
(typ) = 2.5 V.
Table 23
provides the input AC timing specifications for the DDR SDRAM when
V
DD
(typ) = 1.8 V.
Table 24
provides the input AC timing specifications for the DDR SDRAM interface.
Figure 8. Timing for a Reset Configuration Write
Table 22. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface
Parameter
Symbol
Min
Max
Unit
AC input low voltage
V
IL
V
IH
—
MV
REF
– 0.31
—
V
AC input high voltage
MV
REF
+ 0.31
V
Note:
At recommended operating conditions with V
DD
of 2.5
±
5%.
Table 23. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
Parameter
Symbol
Min
Max
Unit
AC input low voltage
V
IL
—
V
REF
– 0.25
V
AC input high voltage
V
IH
V
REF
+ 0.25
—
V
Note:
At recommended operating conditions with V
DD
of 1.8
±
5%.
Table 24. DDR SDRAM Input AC Timing Specifications
Parameter
Symbol
Min
Max
Unit
Controller Skew for MDQS—MDQ/MECC/MDM
1
400 MHz
333 MHz
266 MHz
200 MHz
Notes:
1.
t
CISKEW
represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is
captured with MDQS[n]. Subtract this value from the total timing budget.
2.
At recommended operating conditions with V
DD
(1.8 V or 2.5 V)
±
5%
t
CISKEW
–365
–390
–428
–490
365
390
428
490
ps
ps
ps
ps
PORESET
Input
HRESET
Output (I/O)
SRESET
Output (I/O)
RCW_SRC2,RCW_SRC1,RCW_SRC0,STOP_BS and RCFG_CLKIN_RNG
pins must be valid
1
2
3
Reset configuration write
sequence during this
period.
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