參數(shù)資料
型號: MSC8144
廠商: 飛思卡爾半導體(中國)有限公司
元件分類: 數(shù)字信號處理
英文描述: Quad Core Digital Signal Processor
中文描述: 四核心數(shù)字信號處理器
文件頁數(shù): 59/80頁
文件大?。?/td> 1146K
代理商: MSC8144
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1
Freescale Semiconductor
59
Figure 32
shows the RGMII AC timing and multiplexing diagrams.
GTX_CLK125 reference clock duty cycle
t
G125H
/t
G125
47
53
%
Notes:
1.
2.
3.
4.
At recommended operating conditions with LV
DD
of 2.5 V +/- 5%.
This implies that PC board design will require clocks to be routed with no additional trace delay
For 10 and 100 Mbps, t
RGT
scales to 400 ns +/- 40 ns and 40 ns +/- 4 ns, respectively.
Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long
as the minimum duty cycle is not violated and stretching occurs for no more than three t
RGT
of the lowest speed transitioned
between.
Duty cycle reference is L
Vdd
/2.
This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.
GCR4 should be programmed as 0x00048120.
5.
6.
7.
Figure 32. RGMII AC Timing and Multiplexing s
Table 48. RGMII with No On-Board Delay AC Timing Specifications (continued)
Parameter/Condition
Symbol
Min
Typ
Max
Unit
GTX_CLK
t
RGT
t
RGTH
t
SKEWT
TX_CTL
TXD[8:5]
TXD[7:4]
TXD[9]
TXERR
TXD[4]
TXEN
TXD[3:0]
(At Transmitter)
TXD[8:5][3:0]
TXD[7:4][3:0]
TX_CLK
(At PHY)
RX_CTL
RXD[8:5]
RXD[7:4]
RXD[9]
RXERR
RXD[4]
RXDV
RXD[3:0]
RXD[8:5][3:0]
RXD[7:4][3:0]
RX_CLK
(At PHY)
t
SKEWR
t
SKEWR
t
SKEWT
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