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參數(shù)資料
| 型號(hào)： | MQ80C52CXXX-36SCD |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44 |
| 文件頁(yè)數(shù)： | 94/182頁(yè) |
| 文件大?。?/td> | 2994K |
| 代理商： | MQ80C52CXXX-36SCD |
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19
1477K–AVR–08/10
ATtiny26(L)
EEPROM Data
Register – EEDR
Bit 7..0 – EEDR7..0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
EEPROM Control
Register – EECR
Bit 7..4 – RES: Reserved Bits
These bits are reserved bits in the ATtiny26(L) and will always read as zero.
Bit 3 – EERIE: EEPROM Ready Interrupt Enable
When the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled.
When cleared (zero), the interrupt is disabled. The EEPROM Ready Interrupt generates a con-
stant interrupt when EEWE is cleared (zero).
Bit 2 – EEMWE: EEPROM Master Write Enable
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written.
When EEMWE is set (one), setting EEWE will write data to the EEPROM at the selected
address. If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been set (one)
by software, hardware clears the bit to zero after four clock cycles. See the description of the
EEWE bit for an EEPROM write procedure.
Bit 1 – EEWE: EEPROM Write Enable
The EEPROM Write Enable Signal – EEWE – is the write strobe to the EEPROM. When
address and data are correctly set up, the EEWE bit must be set to write the value in to the
EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no
EEPROM write takes place. The following procedure should be followed when writing the
EEPROM (the order of steps 2 and 3 is unessential):
1. Wait until EEWE becomes zero.
2. Write new EEPROM address to EEAR (optional).
3. Write new EEPROM data to EEDR (optional).
4. Write a logical one to the EEMWE bit in EECR.
5. Within four clock cycles after setting EEMWE, write a logical one to EEWE.
Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the
EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is
interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the
interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared
during all the steps to avoid these problems.
When the access time (typically 8.3 ms) has elapsed, the EEWE bit is cleared (zero) by hard-
ware. The user software can poll this bit and wait for a zero before writing the next byte. When
EEWE has been set, the CPU is halted for two cycles before the next instruction is executed.
Bit 0 – EERE: EEPROM Read Enable
Bit
76543210
$1D ($3D)
MSB
LSB
EEDR
Read/Write
R/W
Initial Value
00000000
Bit
76543
2
1
0
$1C ($3C)
––––
EERIE
EEMWE
EEWE
EERE
EECR
Read/Write
RRRR
R/W
Initial Value
00000
0
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相關(guān)代理商/技術(shù)參數(shù) |
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| MQ82380-20/R | 制造商:Rochester Electronics LLC 功能描述: |
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