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參數(shù)資料
| 型號(hào)： | MQ80C52CXXX-36SCD |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44 |
| 文件頁(yè)數(shù)： | 27/182頁(yè) |
| 文件大?。?/td> | 2994K |
| 代理商： | MQ80C52CXXX-36SCD |
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122
1477K–AVR–08/10
ATtiny26(L)
SPI Serial
Programming
Algorithm
When writing serial data to the ATtiny26, data is clocked on the rising edge of SCK.
When reading data from the ATtiny26, data is clocked on the falling edge of SCK. See Figure
To program and verify the ATtiny26 in the serial programming mode, the following sequence is
recommended (See four byte instruction formats in Table 61):
1. Power-up sequence:
Apply power between VCC and GND while RESET and SCK are set to “0”. In some sys-
tems, the programmer can not guarantee that SCK is held low during Power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
2. Wait for at least 20 ms and enable serial programming by sending the Programming
Enable serial instruction to pin MOSI.
3. The serial programming instructions will not work if the communication is out of synchro-
nization. When in synchronize the second byte ($53), will echo back when issuing the
third byte of the Programming Enable instruction. Whether the echo is correct or not, all 4
bytes of the instruction must be transmitted. If the $53 did not echo back, give RESET a
positive pulse and issue a new Programming Enable command.
4. The Flash is programmed one page at a time. The page size is found in Table 52 on
page 109. The memory page is loaded one byte at a time by supplying the 4 LSB of the
address and data together with the Load Program Memory Page instruction. To ensure
correct loading of the page, the data low byte must be loaded before data high byte is
applied for given address. The Program Memory Page is stored by loading the Write Pro-
gram Memory Page instruction with the 6 MSB of the address. If polling is not used, the
the serial programming interface before the Flash write operation completes can result in
incorrect programming.
5. The EEPROM array is programmed one byte at a time by supplying the address and
data together with the appropriate Write instruction. An EEPROM memory location is first
automatically erased before new data is written. If polling is not used, the user must wait
no $FFs in the data file(s) need to be programmed.
6. Any memory location can be verified by using the Read instruction which returns the con-
tent at the selected address at serial output MISO.
7. At the end of the programming session, RESET can be set high to commence normal
operation.
8. Power-off sequence (if needed):
Set RESET to “1”.
Turn VCC power off.
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