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參數(shù)資料
| 型號(hào)： | MQ80C52CXXX-36SCD |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44 |
| 文件頁數(shù)： | 142/182頁 |
| 文件大小： | 2994K |
| 代理商： | MQ80C52CXXX-36SCD |
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62
1477K–AVR–08/10
ATtiny26(L)
External
Interrupt
The External Interrupt is triggered by the INT0 pin. Observe that, if enabled, the interrupt will trig-
ger even if the INT0 pin is configured as an output. This feature provides a way of generating a
software interrupt. The External Interrupt can be triggered by a falling or rising edge, a pin
change, or a low level. This is set up as indicated in the specification for the MCU Control Regis-
ter – MCUCR. When the External Interrupt is enabled and is configured as level triggered, the
interrupt will trigger as long as the pin is held low.
The changed level is sampled twice by the Watchdog Oscillator clock, and if both these samples
have the required level, the MCU will wake up. The period of the Watchdog Oscillator is 1.0 s
(nominal) at 3.0V and 25°C. The frequency of the Watchdog Oscillator is voltage dependent as
Pin Change
Interrupt
The pin change interrupt is triggered by any change on any I/O pin of Port B and pins PA3, PA6,
and PA7, if the interrupt is enabled and alternate function of the pin does not mask out the inter-
rupt. The bit PCIE1 in GIMSK enables interrupt from pins PB[7:4], PA[7:6], and PA[3]. PCIE0
enables interrupt on digital pins PB[3:0].
The pin change interrupt is different from other interrupts in two ways. First, pin change interrupt
enable bits PCIE1 and PCIE0 also mask the flag if they are not set. The normal operation on
most interrupts is that the flag is always active and only the execution of the interrupt is masked
by the interrupt enable.
Secondly, please note that pin change interrupt is disabled for any pin that is configured as an
alternate function. For example, no pin change interrupt is generated from pins that are config-
ured as AREF, AIN0 or AIN1, OC1A, OC1A, OC1B, OC1B, XTAL1, or XTAL2 in a fuse selected
clock option, Timer0 clocking, or RESET function. See Table 30 for alternate functions which
mask the pin change interrupt and how the function is enabled. For example pin change inter-
rupt on the PB0 is disabled when USI Two-wire mode or USI Three-wire mode or
Timer/Counter1 inverted output compare is enabled.
If the interrupt is enabled, the interrupt will trigger even if the changing pin is configured as an
output. This feature provides a way of generating a software interrupt. Also observe that the pin
change interrupt will trigger even if the pin activity triggers another interrupt, for example the
external interrupt. This implies that one external event might cause several interrupts.
The value of the programmed fuse is “0” and unprogrammed is “1”. Each of the lines enables the
alternate function so “or” function of the lines enables the function.
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