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參數(shù)資料
| 型號(hào)： | MQ80C52CXXX-36SCD |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44 |
| 文件頁(yè)數(shù)： | 168/182頁(yè) |
| 文件大?。?/td> | 2994K |
| 代理商： | MQ80C52CXXX-36SCD |
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86
1477K–AVR–08/10
ATtiny26(L)
ples data at negative and changes the output at positive edges. The USI clock modes
corresponds to the SPI data mode 0 and 1.
Referring to the timing diagram (Figure 46.), a bus transfer involves the following steps:
1. The slave device and master device sets up its data output and, depending on the proto-
col used, enables its output driver (mark A and B). The output is set up by writing the
data to be transmitted to the serial Data Register. Enabling of the output is done by set-
ting the corresponding bit in the port data direction register (DDRB2). Note that point A
and B does not have any specific order, but both must be at least one half SCK cycle
before point C where the data is sampled. This must be done to ensure that the data
setup requirement is satisfied. The 4-bit counter is reset to zero.
2. The master generates a clock pulse by software toggling the SCK line twice (C and D).
The bit value on the slave and master’s data input (DI) pin is sampled by the USI on the
first edge (C), and the data output is changed on the opposite edge (D). The 4-bit counter
will count both edges.
3. Step 2. is repeated eight times for a comlpete register (byte) transfer.
4. After eight clock pulses (i.e., 16 clock edges) the counter will overflow and indicate that
the transfer is completed. The data bytes transferred must now be processed before a
new transfer can be initiated. The overflow interrupt will wake up the processor if it is set
to Idle mode. Depending of the protocol used the slave device can now set its output to
high impedance.
SPI Master Operation
Example
The following code demonstrates how to use the USI module as a SPI master:
SPITransfer:
out
USIDR,r16
ldi
r16,(1<<USIOIF)
out
USISR,r16
ldi
r16,(1<<USIWM0)+(1<<USICS1)+(1<<USICLK)+(1<<USITC)
SPITransfer_loop:
out
USICR,r16
sbis
USISR,USIOIF
rjmp
SPITransfer_loop
in
r16,USIDR
ret
The code is size optimized using only 8 instructions (+ ret). The code example assumes that the
DO and SCK pins are enabled as output in the DDRB Register. The value stored in register r16
prior to the function is called is transferred to the slave device, and when the transfer is com-
pleted the data received from the slave is stored back into the r16 register.
The second and third instructions clears the USI Counter Overflow Flag and the USI counter
value. The fourth and fifth instruction set Three-wire mode, positive edge Shift Register clock,
count at USITC strobe, and toggle SCK (PORTB2). The loop is repeated 16 times.
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| MR80C32-25/883R | 8-BIT, 25 MHz, MICROCONTROLLER, CQCC44 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MQ82370-20 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MQ8238020 | 制造商:Intel 功能描述:CONTROLLER: OTHER |
| MQ82380-20 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MQ82380-20/R | 制造商:Rochester Electronics LLC 功能描述: |
| MQ82592 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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