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參數(shù)資料
| 型號(hào)： | MQ80C52CXXX-36SCD |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44 |
| 文件頁(yè)數(shù)： | 114/182頁(yè) |
| 文件大小： | 2994K |
| 代理商： | MQ80C52CXXX-36SCD |
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37
1477K–AVR–08/10
ATtiny26(L)
Power
Management
and Sleep
Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides various sleep modes allowing the user to tailor the power consump-
tion to the application’s requirements.
To enter any of the four sleep modes, the SE bit in MCUCR must be written to logic one and a
SLEEP instruction must be executed. The SM1, and SM0 bits in the MCUCR Register select
which sleep mode (Idle, ADC Noise Reduction, Power Down, or Stand-by) will be activated by
the SLEEP instruction. See Table 17 for a summary. If an enabled interrupt occurs while the
MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition
to the start-up time, it executes the interrupt routine, and resumes execution from the instruction
following SLEEP. The contents of the Register File and SRAM are unaltered when the device
wakes up from sleep. If a Reset occurs during sleep mode, the MCU wakes up and executes
from the Reset Vector.
Table 19 on page 39 presents the different clock systems in the ATtiny26, and their distribution.
The figure is helpful in selecting an appropriate sleep mode.
MCU Control
Register – MCUCR
The MCU Control Register contains control bits for general MCU functions.
Bits 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny26(L) and always reads as zero.
Bit 6 – PUD: Pull-up Disable
When this bit is set (one), the pull-ups in the I/O ports are disabled even if the DDxn and
PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Con-
figuring the Pin” on page 42 for more details about this feature.
Bit 5 – SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the Sleep mode when the SLEEP instruc-
tion is executed. To avoid the MCU entering the Sleep mode unless it is the programmers
purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the
SLEEP instruction.
Bits 4,3 – SM1/SM0: Sleep Mode Select Bits 1 and 0
These bits select between the four available Sleep modes, as shown in the following table.
For details, refer to the paragraph “Sleep Modes” below.
Bit 2 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny26(L) and always reads as zero.
Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
Bit
765
4321
0
$35 ($55)
–
PUD
SE
SM1
SM0
–
ISC01
ISC00
MCUCR
Read/Write
R
R/W
R
R/W
Initial Value
000
0000
0
Table 17. Sleep Modes
SM1
SM0
Sleep Mode
0
Idle mode
0
1
ADC Noise Reduction mode
1
0
Power-down mode
1
Standby mode
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