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參數(shù)資料
| 型號(hào)： | MQ80C52CXXX-36SCD |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44 |
| 文件頁(yè)數(shù)： | 166/182頁(yè) |
| 文件大?。?/td> | 2994K |
| 代理商： | MQ80C52CXXX-36SCD |
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84
1477K–AVR–08/10
ATtiny26(L)
Bit 3..2 – USICS1..0: Clock Source Select
These bits set the clock source for the Shift Register and counter. The data output latch ensures
that the output is changed at the opposite edge of the sampling of the data input (DI/SDA) when
using external clock source (SCK/SCL). When software strobe or Timer0 overflow clock option is
selected the output latch is transparent and therefore the output is changed immediately. Clear-
ing the USICS1..0 bits enables software strobe option. When using this option, writing a one to
the USICLK bit clocks both the Shift Register and the counter. For external clock source
(USICS1 = 1), the USICLK bit is no longer used as a strobe, but selects between external clock-
ing, and software clocking by the USITC strobe bit.
Table 40 shows the relationship between the USICS1..0 and USICLK setting and clock source
used for the Shift Register and the 4-bit counter.
Bit 1 – USICLK: Clock Strobe
Writing a one to this bit location strobes the Shift Register to shift one step and the counter to
increment by one provided that the USICS1..0 bits are set to zero and by doing so selects the
software clock strobe option. The output will change immediately when the clock strobe is exe-
cuted i.e. in the same instruction cycle. The value shifted into the Shift Register is sampled the
previous instruction cycle. The bit will be read as zero.
When an external clock source is selected (USICS1 = 1), the USICLK function is changed from
a clock strobe to a Clock Select Register. Setting the USICLK bit in this case will select the
USITC strobe bit as clock source for the 4-bit counter (see Table 40).
Bit 0 – USITC: Toggle Clock Port Pin
Writing a one to this bit location toggles the PORTB2 (SCK/SCL) value from either from 0 to 1, or
1 to 0. The toggling is independent of the DDRB2 setting, but if the PORTB2 value is to be
shown on the pin the DDRB2 must be set as output (to one). This feature allows easy clock gen-
eration when implementing master devices. The bit will be read as zero.
When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writ-
ing to the USITC strobe bit will directly clock the 4-bit counter. This allows an early detection of
when the transfer is done when operating as a master device.
Table 40. Relations between the USICS1..0 and USICLK Setting
USICS1
USICS0
USICLK
Shift Register Clock
Source
4-bit Counter Clock
Source
0
No Clock
0
1
Software clock strobe
(USICLK)
Software clock strobe
(USICLK)
0
1
X
Timer/Counter0 overflow
1
0
External, positive edge
External, both edges
1
0
External, negative edge
External, both edges
1
0
1
External, positive edge
Software clock strobe
(USITC)
1
External, negative edge
Software clock strobe
(USITC)
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