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參數(shù)資料
| 型號： | MQ80C52CXXX-36SCD |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44 |
| 文件頁數(shù)： | 138/182頁 |
| 文件大?。?/td> | 2994K |
| 代理商： | MQ80C52CXXX-36SCD |
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59
1477K–AVR–08/10
ATtiny26(L)
Bit 5 – PCIE1: Pin Change Interrupt Enable1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the
interrupt pin change is enabled on analog pins PB[7:4], PA[7:6] and PA[3]. Unless the alternate
function masks out the interrupt, any change on the pin mentioned before will cause an interrupt.
The corresponding interrupt of Pin Change Interrupt Request is executed from program memory
address $002. See also “Pin Change Interrupt” on page 62.
Bit 4– PCIE0: Pin Change Interrupt Enable0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the
interrupt pin change is enabled on digital pins PB[3:0]. Unless the alternate function masks out
the interrupt, any change on the pin mentioned before will cause an interrupt. The corresponding
interrupt of Pin Change Interrupt Request is executed from program memory address $002. See
Bits 3..0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26(L) and always read as zero.
General Interrupt Flag
Register – GIFR
Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny26(L) and always reads as zero.
Bit 6 – INTF0: External Interrupt Flag0
When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-
bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the Interrupt Vector at
address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag
can be cleared by writing a logical one to it. The flag is always cleared when INT0 is configured
as level interrupt.
Bit 5 – PCIF: Pin Change Interrupt Flag
When an event on pins PB[7:0], PA[7:6], or PA[3] triggers an interrupt request, PCIF becomes
set (one). PCIE1 enables interrupt from analog pins PB[7:4], PA[7:6], and PA[3]. PCIE0 enables
interrupt on digital pins PB[3:0]. Note that pin change interrupt enable bits PCIE1 and PCIE0
also mask the flag if they are not set. For example, if PCIE0 is cleared, a pin change on PB[3:0]
does not set PCIF. If an alternate function is enabled on a pin, PCIF is masked from that individ-
ual pin. If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the MCU will jump to the
Interrupt Vector at address $002. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. See also “Pin Change Inter-
Bits 4..0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26(L) and always read as zero.
Timer/Counter
Interrupt Mask
Register – TIMSK
Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny26(L) and always reads as zero.
Bit
765
4321
0
$3A ($5A)
–
INTF0
PCIF
––––
–
GIFR
Read/Write
R
R/W
R
Initial Value
000
0000
0
Bit
7
6
5
4
3
2
1
0
$39 ($59)
–
OCIE1A
OCIE1B
–
TOIE1
TOIE0
–
TIMSK
Read/Write
R
R/W
R
R/W
R
Initial Value
0
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