參數(shù)資料
型號: MPC8544VTARJ
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 533 MHz, MICROPROCESSOR, PBGA783
封裝: 29 X 29 MM, 1 MM PITCH, LEAD FREE, PLASTIC, FC-PBGA-783
文件頁數(shù): 44/112頁
文件大小: 1294K
代理商: MPC8544VTARJ
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
37
Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 17 provides the AC test load for eTSEC.
Figure 17. eTSEC AC Test Load
Figure 18 shows the MII receive AC timing diagram.
Figure 18. MII Receive AC Timing Diagram
8.4.4
TBI AC Timing Specifications
This section describes the TBI transmit and receive AC timing specifications.
8.4.4.1
TBI Transmit AC Timing Specifications
Table 35 provides the TBI transmit AC timing specifications.
RX_CLK clock fall time (80%–20%)
tMRXF
1.0
4.0
ns
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K)
going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input
signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general,
the clock reference symbol representation is based on three letters representing the clock of a particular functional. For
example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used
with the appropriate letter: R (rise) or F (fall).
Table 35. TBI Transmit AC Timing Specifications
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
Notes
GTX_CLK clock period
tGTX
—8.0
ns
GTX_CLK to TCG[9:0] delay time
tTTKHDX
0.2
5.0
ns
2
Table 34. MII Receive AC Timing Specifications (continued)
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
Notes
Output
Z0 = 50 Ω
LVDD/2
RL = 50 Ω
RX_CLK
RXD[3:0]
tMRDXKL
tMRX
tMRXH
tMRXR
tMRXF
RX_DV
RX_ER
tMRDVKH
Valid Data
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