參數(shù)資料
型號(hào): MPC8544VTARJ
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 533 MHz, MICROPROCESSOR, PBGA783
封裝: 29 X 29 MM, 1 MM PITCH, LEAD FREE, PLASTIC, FC-PBGA-783
文件頁(yè)數(shù): 10/112頁(yè)
文件大?。?/td> 1294K
代理商: MPC8544VTARJ
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
107
System Design Information
21.10 Guidelines for High-Speed Interface Termination
21.10.1 SerDes Interface Entirely Unused
If the high-speed SerDes interface is not used at all, the unused pin should be terminated as described in
this section. However, the SerDes must always have power applied to its supply pins.
The following pins must be left unconnected (float):
SD_TX[7:0]
The following pins must be connected to GND:
SD_RX[7:0]
SD_REF_CLK
21.10.2 SerDes Interface Partly Unused
If only part of the high speed SerDes interface pins are used, the remaining high-speed serial I/O pins
should be terminated as described in this section.
The following pins must be left unconnected (float) if not used:
SD_TX[7:0]
The following pins must be connected to GND if not used:
SD_RX[7:0]
SD_REF_CLK
21.11 Guideline for PCI Interface Termination
PCI termination if not used at all.
Option 1
If PCI arbiter is enabled during POR,
All AD pins will be driven to the stable states after POR. Therefore, all ADs pins can be floating.
All PCI control pins can be grouped together and tied to OVDD through a single 10-kΩ resistor.
It is optional to disable PCI block through DEVDISR register after POR reset.
Option 2
If PCI arbiter is disabled during POR,
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