參數(shù)資料
型號(hào): MPC8544VTARJ
廠商: FREESCALE SEMICONDUCTOR INC
元件分類(lèi): 微控制器/微處理器
英文描述: 32-BIT, 533 MHz, MICROPROCESSOR, PBGA783
封裝: 29 X 29 MM, 1 MM PITCH, LEAD FREE, PLASTIC, FC-PBGA-783
文件頁(yè)數(shù): 20/112頁(yè)
文件大?。?/td> 1294K
代理商: MPC8544VTARJ
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
15
Input Clocks
4.1.1
SYSCLK and Spread Spectrum Sources
Spread spectrum clock sources are an increasingly popular way to control electromagnetic interference emissions
(EMI) by spreading the emitted noise to a wider spectrum and reducing the peak noise magnitude in order to meet
industry and government requirements. These clock sources intentionally add long-term jitter in order to diffuse the
EMI spectral content. The jitter specification given in Table 6 considers short-term (cycle-to-cycle) jitter only and
the clock generator’s cycle-to-cycle output jitter should meet the MPC8544E input cycle-to-cycle jitter requirement.
Frequency modulation and spread are separate concerns, and the MPC8544E is compatible with spread spectrum
sources if the recommendations listed in Table 7 are observed.
It is imperative to note that the processor’s minimum and maximum SYSCLK, core, and VCO frequencies
must not be exceeded regardless of the type of clock source. Therefore, systems in which the processor is
operated at its maximum rated e500 core frequency should avoid violating the stated limits by using
down-spreading only.
4.2
Real-Time Clock Timing
The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then
used as an input to the counters of the PIC and the TimeBase unit of the e500. There is no jitter
specification. The minimum pulse width of the RTC signal should be greater than 2 × the period of the
CCB clock. That is, minimum clock high time is 2
× t
CCB, and minimum clock low time is 2 × tCCB. There
is no minimum RTC frequency; RTC may be grounded if not needed.
4.3
eTSEC Gigabit Reference Clock Timing
Table 8 provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications for
the MPC8544E.
Table 7. Spread Spectrum Clock Source Recommendations
At recommended operating conditions. See Table 2.
Parameter
Min
Max
Unit
Notes
Frequency modulation
20
60
kHz
Frequency spread
0
1.0
%
1
Note:
1. SYSCLK frequencies resulting from frequency spreading, and the resulting core and VCO
frequencies, must meet the minimum and maximum specifications given in Table 6.
Table 8. EC_GTX_CLK125 AC Timing Specifications
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
EC_GTX_CLK125 frequency
fG125
—125
MHz
EC_GTX_CLK125 cycle time
tG125
—8
ns
EC_GTX_CLK rise and fall time
LVDD, TVDD = 2.5 V
LVDD, TVDD = 3.3 V
tG125R/tG125F
——
0.75
1.0
ns
1
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