參數(shù)資料
型號: MPC8544VTARJ
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 533 MHz, MICROPROCESSOR, PBGA783
封裝: 29 X 29 MM, 1 MM PITCH, LEAD FREE, PLASTIC, FC-PBGA-783
文件頁數(shù): 25/112頁
文件大?。?/td> 1294K
代理商: MPC8544VTARJ
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
2
Freescale Semiconductor
MPC8544E Overview
Figure 1. MPC8544E Block Diagram
— Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit)
floating-point instructions that use the 64-bit GPRs.
— 36-bit real addressing
— Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set
for single-precision (32-bit) floating-point instructions.
— Memory management unit (MMU). Especially designed for embedded applications. Supports
4-Kbyte–4-Gbyte page sizes.
— Enhanced hardware and software debug support
— Performance monitor facility that is similar to, but separate from, the device performance
monitor
The e500 defines features that are not implemented on this device. It also generally defines some features
that this device implements more specifically. An understanding of these differences can be critical to
ensure proper operations.
256-Kbyte L2 cache/SRAM
— Flexible configuration
— Full ECC support on 64-bit boundary in both cache and SRAM modes
— Cache mode supports instruction caching, data caching, or both.
— External masters can force data to be allocated into the cache through programmed memory
ranges or special transaction types (stashing).
– 1, 2, or 4 ways can be configured for stashing only.
MPC8544E
e500 Core
32-Kbyte
D-Cache
32-Kbyte
I-Cache
256-Kbyte
L2
Cache
XOR
Acceleration
Local
64-Bit
DDR/DDR2
SDRAM
Bus
Controller
OpenPIC
Security
Acceleration
32-Bit
Gigabit
Ethernet
PCI
DMA
Performance
Monitor
DUART
2x I2C
Coherency
Module
e500
Express
PCI
Express
PCI
Express
x1
x4/x2/x1
SGMII
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