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參數(shù)資料
| 型號： | MPC604E |
| 廠商： | Motorola, Inc. |
| 英文描述： | PowerPC 604e-TM RISC Microprocessor Technical Summary |
| 中文描述： | 的PowerPC 604e -商標RISC微處理器技術總結 |
| 文件頁數(shù)： | 9/34頁 |
| 文件大?。?/td> | 117K |
| 代理商： | MPC604E |
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PowerPC 604e RISC Microprocessor Technical Summary
9
1.2.1 Instruction Flow
Several units on the 604e ensure the proper flow of instructions and operands and guarantee the correct
update of the architectural machine state. These units include the following:
Fetch unit—Using the next sequential address or the address supplied by the BPU when a branch
is predicted or resolved, the fetch unit supplies instructions to the eight-word instruction buffer.
Dispatch unit—The decode/dispatch unit decodes instructions and dispatches them to the
appropriate execution unit. During dispatch, operands are provided to the execution unit (or
reservation station) from the register files, rename buffers, and result buses.
Branch processing unit (BPU)—Provides the fetcher with predicted target instructions when a
branch is predicted (and a mispredict recovery address if a branch is incorrectly predicted).
Condition register unit (CRU)—The CRU executes all condition register logical and flow control
instructions. The CRU shares the dispatch bus with the BPU only one condition register or branch
instruction can be issued per clock cycle.
Completion unit—The completion unit retires executed instructions in program order and controls
the updating of the architectural machine state.
1.2.2 Fetch Unit
The fetch unit provides instructions to the eight-entry instruction queue by accessing the on-chip instruction
cache. Typically, the fetch unit continues fetching sequentially as many as four instructions at a time.
The address of the next instruction to be fetched is determined by several conditions, which are prioritized
as follows:
1. Detection of an exception. Instruction fetching begins at the exception vector.
2. The BPU recovers from an incorrect prediction when a branch instruction is in the execute stage.
Undispatched instructions are flushed and fetching begins at the correct target address.
3. The BPU recovers from an incorrect prediction when a branch instruction is in the dispatch stage.
Subsequent instructions are flushed and fetching begins at the correct target address.
4. The BPU recovers from an incorrect prediction when a branch instruction is in the decode stage.
Subsequent instructions are flushed and fetching begins at the correct target address.
5. A fetch address is found in the BTAC. As a cache block is fetched, the branch target address cache
(BTAC) and the branch history table (BHT) are searched with the fetch address. If it is found in the
BTAC, the target address from the BTAC is the first candidate for being the next fetch address.
6. If none of the previous conditions exists, the instruction is fetched from the next sequential address.
1.2.3 Decode/Dispatch Unit
The decode/dispatch unit provides the logic for decoding instructions and issuing them to the appropriate
execution unit. The eight-entry instruction queue consists of two four-entry queues—a decode queue (DEQ)
and a dispatch queue (DISQ).
The decode logic decodes the four instructions in the decode queue. For many branch instructions, these
decoded instructions along with the bits in the BHT, are used during the decode stage for branch correction.
The dispatch logic decodes the instructions in the DISQ for possible dispatch. The dispatch logic resolves
unconditional branch instructions and predicts conditional branch instructions using the branch decode
logic, the BHT, and values in the CTR.
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