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參數(shù)資料
| 型號： | MPC604E |
| 廠商： | Motorola, Inc. |
| 英文描述： | PowerPC 604e-TM RISC Microprocessor Technical Summary |
| 中文描述： | 的PowerPC 604e -商標RISC微處理器技術(shù)總結(jié) |
| 文件頁數(shù)： | 5/34頁 |
| 文件大?。?/td> | 117K |
| 代理商： | MPC604E |
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PowerPC 604e RISC Microprocessor Technical Summary
5
— Support for additional processor/bus clock ratios (5:2 and 4:1). Configuration of the processor/
bus clock ratios is displayed through a new 604e-specific register, HID1.
— To support the changes in the clocking configuration, different precharge timings for the ABB,
DBB, ARTRY, and SHD signals are implemented internally by the processor. The precharge
timings for ARTRY and SHD can be disabled by setting HID0[7].
— No-DRTRY mode. In addition to the normal and fast L2 modes implemented on the 604, a no-
DRTRY mode is implemented on the 604e that improves performance on read operations for
systems that do not use the DRTRY signal. No-DRTRY mode makes read data available to the
processor one bus clock cycle sooner than in normal mode
signal is no longer sampled as part of a qualified bus grant.
Full hardware support for little-endian accesses. Little-endian accesses take alignment exceptions
for only the same set of causes as big-endian accesses. Accesses that cross a word boundary require
two accesses with the lower-addressed word accessed first.
Additional enhancements to the performance monitor.
.
In no-DRTRY mode, the DRTRY
1.1.2 Overview of the PowerPC 604e Microprocessor Features
Major features of the 604e are as follows:
High-performance, superscalar microprocessor
— As many as four instructions can be issued per clock
— As many as seven instructions can start executing per clock (including three integer
instructions)
— Single-clock-cycle execution for most instructions
Seven independent execution units and two register files
— BPU featuring dynamic branch prediction
– Two-entry reservation station
– Out-of-order execution through two branches
– Shares dispatch bus with CRU
– 64-entry fully-associative branch target address cache (BTAC). In the 604e, the BTAC can
be disabled and invalidated.
– 512-entry branch history table (BHT) with two bits per entry for four levels of prediction—
not-taken, strongly not-taken, taken, strongly taken
— Condition register logical unit
– Two-entry reservation station
– Shares dispatch bus with BPU
— Two single-cycle IUs (SCIUs) and one multiple-cycle IU (MCIU)
– Instructions that execute in the SCIU take one cycle to execute; most instructions that
execute in the MCIU take multiple cycles to execute.
– Each SCIU has a two-entry reservation station to minimize stalls
– The MCIU has a single-entry reservation station and provides early exit (three cycles)
for 16- x 32-bit and overflow operations.
– Thirty-two GPRs for integer operands
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