參數(shù)資料
型號： MPC604E
廠商： Motorola, Inc.
英文描述： PowerPC 604e-TM RISC Microprocessor Technical Summary
中文描述： 的PowerPC 604e -商標(biāo)RISC微處理器技術(shù)總結(jié)
文件頁數(shù)： 19/34頁
文件大?。?/td> 117K
代理商： MPC604E
PowerPC 604e RISC Microprocessor Technical Summary
19
The 604e supports the following processor-to-bus clock frequency ratios—1:1, 3:2, 2:1, 5:2, 3:1, and 4:1,
although not all ratios are available for all frequencies. Configuration of the processor/bus clock ratios is
displayed through a 604e-specific register, HID1.
Part 2 PowerPC 604e Microprocessor:
Implementation
The PowerPC architecture is derived from the IBM POWER architecture (Performance Optimized with
Enhanced RISC architecture). The PowerPC architecture shares the benefits of the POWER architecture
optimized for single-chip implementations. The PowerPC architecture design facilitates parallel instruction
execution and is scalable to take advantage of future technological gains.
This section describes the PowerPC architecture in general, and specific details about the implementation
of the 604e as a low-power, 32-bit member of the PowerPC processor family.
Features—Section 2.1, “Features,” describes general features that the 604e shares with the
PowerPC microprocessor family.
Registers and programming model—Section 2.1.1, “Registers and Programming Model,” describes
the registers for the operating environment architecture common among PowerPC processors and
describes the programming model. It also describes the additional registers that are unique to the
604e.
Instruction set and addressing modes—Section 2.1.2, “Instruction Set and Addressing Modes,”
describes the PowerPC instruction set and addressing modes for the PowerPC operating
environment architecture, and defines and describes the PowerPC instructions implemented in the
604e.
Exception model—Section 2.1.3, “Exception Model,” describes the exception model of the
PowerPC operating environment architecture and the differences in the 604e exception model.
Instruction timing—Section 2.1.4, “Instruction Timing,” provides a general description of the
instruction timing provided by the parallel execution supported by the PowerPC architecture and
the 604e.
2.1 Features
The 604e is a high-performance, superscalar PowerPC implementation of the PowerPC architecture. Like
other PowerPC processors, it adheres to the PowerPC architecture specifications but also has additional
features not defined by the architecture. These features do not affect software compatibility. The PowerPC
architecture allows optimizing compilers to schedule instructions to maximize performance through
efficient use of the PowerPC instruction set and register model. The multiple, independent execution units
in the 604e allow compilers to maximize parallelism and instruction throughput. Compilers that take
advantage of the flexibility of the PowerPC architecture can additionally optimize instruction processing of
the PowerPC processors.
The following sections summarize the features of the 604e, including both those that are defined by the
architecture and those that are unique to the 604e implementation.
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