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參數(shù)資料
| 型號： | MPC604E |
| 廠商： | Motorola, Inc. |
| 英文描述： | PowerPC 604e-TM RISC Microprocessor Technical Summary |
| 中文描述： | 的PowerPC 604e -商標RISC微處理器技術總結 |
| 文件頁數(shù)： | 17/34頁 |
| 文件大小： | 117K |
| 代理商： | MPC604E |
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PowerPC 604e RISC Microprocessor Technical Summary
17
Data arbitration signals—The 604e uses these signals to arbitrate for data bus mastership.
Data transfer signals—These signals, which consist of the data bus, data parity, and data parity error
signals, are used to transfer the data and to ensure the integrity of the transfer.
Data termination signals—Data termination signals are required after each data beat in a data
transfer. In a single-beat transaction, the data termination signals also indicate the end of the tenure,
while in burst accesses, the data termination signals apply to individual beats and indicate the end
of the tenure only after the final data beat. They also indicate whether a condition exists that requires
the data phase to be repeated.
Interrupt signals—These signals include the interrupt signal, checkstop signals, and both soft- and
hard-reset signals. These signals are used to interrupt and, under various conditions, to reset the
processor.
Processor state signals—These two signals are used to set the reservation coherency bit and set the
size of the 604e’s output buffers.
Miscellaneous signals—These signals are used in conjunction with such resources as secondary
caches and the time base facility.
COP interface signals—The common on-chip processor (COP) unit is the master clock control unit
and it provides a serial interface to the system for performing built-in self test (BIST).
Clock signals—These signals determine the system clock frequency. These signals can also be used
to synchronize multiprocessor systems.
NOTE
A bar over a signal name indicates that the signal is active low—for
example, ARTRY (address retry) and TS (transfer start). Active-low
signals are referred to as asserted (active) when they are low and negated
when they are high. Signals that are not active-low, such as AP0–AP3
(address bus parity signals) and TT0–TT4 (transfer type signals) are
referred to as asserted when they are high and negated when they are low.
1.2.11.3 Signal Configuration
Figure 5 illustrates the logical pin configuration of the 604e, showing how the signals are grouped.
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