參數(shù)資料
型號(hào)： MPC604E
廠商： Motorola, Inc.
英文描述： PowerPC 604e-TM RISC Microprocessor Technical Summary
中文描述： 的PowerPC 604e -商標(biāo)RISC微處理器技術(shù)總結(jié)
文件頁(yè)數(shù)： 25/34頁(yè)
文件大?。?/td> 117K
代理商： MPC604E
PowerPC 604e RISC Microprocessor Technical Summary
25
— Logical instructions
— Integer rotate and shift instructions
Floating-point instructions—These include floating-point computational instructions, as well as
instructions that affect the FPSCR. Floating-point instructions include the following:
— Floating-point arithmetic instructions
— Floating-point multiply/add instructions
— Floating-point rounding and conversion instructions
— Floating-point compare instructions
— Floating-point move instructions
— Floating-point status and control instructions
— Optional floating-point instructions (listed with the optional instructions below)
The 604e supports all IEEE 754-1985 floating-point data types (normalized, denormalized, NaN,
zero, and infinity) in hardware, eliminating the latency incurred by software exception routines.
The PowerPC architecture also supports a non-IEEE mode, controlled by a bit in the FPSCR. In this
mode, denormalized numbers, NaNs, and some IEEE invalid operations are not required to conform
to IEEE standards and can execute faster. Note that all single-precision arithmetic instructions are
performed using a double-precision format. The floating-point pipeline is a single-pass
implementation for double-precision products. Except for divide instructions, a single-precision
instruction using only single-precision operands in double-precision format performs the same as
its double-precision equivalent.
Load/store instructions—These include integer and floating-point load and store instructions.
— Integer load and store instructions
— Integer load and store multiple instructions
— Integer load and store string instructions
— Floating-point load and store
Flow control instructions—These include branching instructions, condition register logical
instructions, trap instructions, and other instructions that affect the instruction flow.
— Branch and trap instructions
— System call and
rfi
instructions
— Condition register logical instructions
Synchronization instructions—The PowerPC architecture defines instructions for memory
synchronizing, especially useful for multiprocessing:
— Load and store with reservation instructions—These UISA-defined instructions provide
primitives for synchronization operations such as test and set, compare and swap, and compare
memory.
— The Synchronize (
sync
) instruction—This UISA-defined instruction is useful for
synchronizing load and store operations on a memory bus that is shared by multiple devices.
— The Enforce In-Order Execution of I/O (
eieio
) instruction—The
eieio
instruction, defined by
the VEA, can be used instead of the
sync
instruction when only memory references seen by
I/O devices need to be ordered.
— The Instruction Synchronize (
isync
) instruction waits until all previous instructions have
completed and discards and then refetches any subsequent instructions to ensure that those
instructions complete in the context established by the previous instructions.
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