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參數(shù)資料
| 型號： | MPC604E |
| 廠商： | Motorola, Inc. |
| 英文描述： | PowerPC 604e-TM RISC Microprocessor Technical Summary |
| 中文描述： | 的PowerPC 604e -商標RISC微處理器技術(shù)總結(jié) |
| 文件頁數(shù)： | 22/34頁 |
| 文件大?。?/td> | 117K |
| 代理商： | MPC604E |
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PowerPC 604e RISC Microprocessor Technical Summary
PowerPC processors have two levels of privilege—supervisor mode of operation (typically used by the
operating environment) and one that corresponds to the user mode of operation (used by application
software). As shown in Figure 6, the programming model incorporates 32 GPRs, 32 FPRs, special-purpose
registers (SPRs), and several miscellaneous registers. Note that each PowerPC implementation has its own
unique set of implementation-dependent registers that are typically used for debugging, configuration, and
other implementation-specific operations.
Some registers are accessible only by supervisor-level software. This division allows the operating system
to control the application environment (providing virtual memory and protecting operating-system and
critical machine resources). Instructions that control the state of the processor, the address translation
mechanism, and supervisor registers can be executed only when the processor is in supervisor mode.
The following sections summarize the PowerPC registers that are implemented in the 604e.
2.1.1.1 General-Purpose Registers (GPRs)
The PowerPC architecture defines 32 user-level, general-purpose registers (GPRs). These registers are
either 32 bits wide in 32-bit PowerPC implementations and 64 bits wide in 64-bit PowerPC
implementations. The 604e also has 12 GPR rename buffers, which provide a way to buffer data intended
for the GPRs, reducing stalls when the results of one instruction are required by a subsequent instruction.
The use of rename buffers is not defined by the PowerPC architecture, and they are transparent to the user
with respect to the architecture. The GPRs and their associated rename buffers serve as the data source or
destination for instructions executed in the IUs.
2.1.1.2 Floating-Point Registers (FPRs)
The PowerPC architecture also defines 32 floating-point registers (FPRs). These 64-bit registers typically
are used to provide source and target operands for user-level, floating-point instructions. As with the GPRs,
the 604e also has eight FPR rename buffers, which provide a way to buffer data intended for the FPRs,
reducing stalls when the results of one instruction are required by a subsequent instruction. The rename
buffers are not defined by the PowerPC architecture. The FPRs and their associated rename buffers can
contain data objects of either single- or double-precision floating-point formats.
2.1.1.3 Condition Register (CR)
The CR is a 32-bit user-level register that consists of eight four-bit fields that reflect the results of certain
operations, such as move, integer and floating-point compare, arithmetic, and logical instructions, and
provide a mechanism for testing and branching. The 604e also has eight CR rename buffers, which provide
a way to buffer data intended for the CR. The rename buffers are not defined by the PowerPC architecture.
2.1.1.4 Floating-Point Status and Control Register (FPSCR)
The floating-point status and control register (FPSCR) is a user-level register that contains all exception
signal bits, exception summary bits, exception enable bits, and rounding control bits needed for compliance
with the IEEE 754 standard.
2.1.1.5 Machine State Register (MSR)
The machine state register (MSR) is a supervisor-level register that defines the state of the processor. The
contents of this register are saved when an exception is taken and restored when the exception handling
completes. The 604e implements the MSR as a 32-bit register; 64-bit PowerPC processors use a 64-bit MSR
that provide a superset of the 32-bit functionality.
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