- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371134 > MPC604E (Motorola, Inc.) PowerPC 604e-TM RISC Microprocessor Technical Summary PDF資料下載
參數(shù)資料
| 型號(hào)： | MPC604E |
| 廠商： | Motorola, Inc. |
| 英文描述： | PowerPC 604e-TM RISC Microprocessor Technical Summary |
| 中文描述： | 的PowerPC 604e -商標(biāo)RISC微處理器技術(shù)總結(jié) |
| 文件頁數(shù)： | 32/34頁 |
| 文件大?。?/td> | 117K |
| 代理商： | MPC604E |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁當(dāng)前第32頁第33頁第34頁
32
PowerPC 604e RISC Microprocessor Technical Summary
Figure 7. Pipeline Diagram
The common pipeline stages are as follows:
Instruction fetch (IF)—During the IF stage, the fetch unit loads the decode queue (DEQ) with
instructions from the instruction cache and determines from what address the next instruction
should be fetched.
Instruction decode (ID)—During the ID stage, all time-critical decoding is performed on
instructions in the dispatch queue (DISQ). The remaining decode operations are performed during
the instruction dispatch stage.
Instruction dispatch (DS)—During the dispatch stage, the decoding that is not time-critical is
performed on the instructions provided by the previous ID stage. Logic associated with this stage
determines when an instruction can be dispatched to the appropriate execution unit. At the end of
the DS stage, instructions and their operands are latched into the execution input latches or into the
unit’s reservation station. Logic in this stage allocates resources such as the rename registers and
reorder buffer entries.
Execute (E)—While the execution stage is viewed as a common stage in the 604e instruction
pipeline, the instruction flow is split among the seven execution units, some of which consist of
multiple pipelines. An instruction may enter the execute stage from either the dispatch stage or the
execution unit’s dedicated reservation station.
At the end of the execute stage, the execution unit writes the results into the appropriate rename
buffer entry and notifies the completion stage that the instruction has finished execution.
Decode (ID)
Complete (C)
Writeback (W)
(Four-instruction dispatch per clock in
any combination)
SCIU1
Execute Stage
SCIU2
FPU
Fetch (IF)
Dispatch (DS)
LSU
MCIU
BPU
CPU
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC755BPX350LE | RISC Microprocessor Hardware Specifications |
| MPC755BRX350LE | RISC Microprocessor Hardware Specifications |
| MPC755CPX400LE | RISC Microprocessor Hardware Specifications |
| MPC755CRX400LE | RISC Microprocessor Hardware Specifications |
| MPC755 | RISC Microprocessor Hardware Specifications |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC6071 | 制造商:International Rectifier 功能描述: |
| MPC616 | 制造商:Hammond Manufacturing 功能描述:6" X 16" MAGNET PANEL COVER |
| MPC-628-011B | 制造商:FCI 功能描述: |
| MPC628726C | 制造商:FCI 功能描述:- Bulk |
| MPC-6800 | 制造商:AAEON 制造商全稱:AAEON 功能描述:Intel Ultra Low Voltage Celeron Processor |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。