參數(shù)資料
型號(hào)： MPC604E
廠商： Motorola, Inc.
英文描述： PowerPC 604e-TM RISC Microprocessor Technical Summary
中文描述： 的PowerPC 604e -商標(biāo)RISC微處理器技術(shù)總結(jié)
文件頁(yè)數(shù)： 8/34頁(yè)
文件大小： 117K
代理商： MPC604E
8
PowerPC 604e RISC Microprocessor Technical Summary
Performance monitor can be used to help in debugging system designs and improving software
efficiency, especially in multiprocessor systems.
In-system testability and debugging features through JTAG boundary-scan capability
1.2 PowerPC 604e Microprocessor Hardware
Implementation
This section provides an overview of the 604e’s hardware implementation, including descriptions of the
functional units, shown in Figure 2, the cache implementation, MMU, and the system interface.
Note that Figure 2 provides a more detailed block diagram than that presented in Figure 1—showing the
additional data paths that contribute to the improved efficiency in instruction execution and more clearly
shows the relationships between execution units and their associated register files.
Figure 2. Block Diagram—Internal Data Paths
Fetch Unit
Branch
correction
(Four-instruction
dispatch)
Dispatch Unit
BPU
32-Kbyte data cache
4-way, 8 words/block
Completion
Unit
Instruction dispatch buses
Result status buses
LSU
MCIU
SCIU
SCIU
FPU
Result buses
Operand buses
RS(2)
RS(1)
RS(2)
RS(2)
RS(2)
CRU
RS(2)
3
F
R
B
3
RS(2)
G
R
B
GPR operand buses
GPR result buses
CR result bus
FPR operand buses
FPR result buses
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