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參數(shù)資料
| 型號(hào)： | MPC603E7TED |
| 廠商： | Motorola, Inc. |
| 英文描述： | PowerPC 603e RISC Microprocessor |
| 中文描述： | RISC微處理器的PowerPC 603e |
| 文件頁數(shù)： | 23/36頁 |
| 文件大小： | 551K |
| 代理商： | MPC603E7TED |
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PID7t-603e Hardware Specifications
For More Information On This Product,
Go to: www.freescale.com
23
System Design Information
1.8 System Design Information
This section provides electrical and thermal design recommendations for successful application of the 603e.
1.8.1 PLL ConTguration
The 603e PLL is conTgured by the PLL_CFG[0D3] signals. For a given SYSCLK (bus) frequency, the PLL
conTguration signals set the internal CPU and VCO frequency of operation. The PLL conTguration for the
PID7t-603e is shown in Table 12 for nominal frequencies.
Table 12. PLL Configuration
PLL_CFG[0:3]
CPU Frequency in MHz (VCO Frequency in MHz)
Bus-to-Core
Multiplier
Core-to
VCO
Multiplier
Bus
25 MHz
Bus
33.33 MHz
Bus
40 MHz
Bus
50 MHz
Bus
60 MHz
Bus
66.67 MHz
Bus
75 MHz
0100
2x
2x
—
—
—
—
—
—
150
(300)
0101
2x
4x
—
—
80
4
(320)
100
(400)
120
(480)
133
(532)
150
(600)
0110
2.5x
2x
—
—
—
—
150
(300)
166
(333)
187
(375)
1000
3x
2x
—
—
—
150
(300)
180
(360)
200
(400)
225
(450)
1110
3.5x
2x
—
—
—
175
(350)
210
(420)
233 (466)
263
(525)
1010
4x
2x
—
—
160
(320)
200
(400)
240
(480)
267 (533)
300
(600)
0111
4.5x
2x
—
150
(300)
180
(360)
225
(450)
270
(540)
300 (600)
—
1011
5x
2x
—
166
(333)
200
(400)
250
(500)
300
(600)
—
—
1001
5.5x
2x
—
183 (366)
220
(440)
275
(550)
—
—
—
1101
6x
2x
150
(300)
200
(400)
240
(480)
300
(600)
—
—
—
0011
PLL bypass
1111
Clock off
Notes
:
1. Some PLL configurations may select bus, CPU, or VCO frequencies which are not supported; see
Section 1.4.2.1, “Clock AC Specifications,” for valid SYSCLK and VCO frequencies.
2. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and
the bus mode is set for 1:1 mode operation. This mode is intended for factory use only.
Note
: The AC timing specifications given in this document do not apply in PLL-bypass mode.
3. In clock-off mode, no clocking occurs inside the 603e regardless of the SYSCLK input.
4. 80 MHz operation is not supported for the PBGA package (see Table 7)
F
Freescale Semiconductor, Inc.
n
.
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