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參數(shù)資料
| 型號(hào)： | MPC603E7TED |
| 廠商： | Motorola, Inc. |
| 英文描述： | PowerPC 603e RISC Microprocessor |
| 中文描述： | RISC微處理器的PowerPC 603e |
| 文件頁(yè)數(shù)： | 13/36頁(yè) |
| 文件大?。?/td> | 551K |
| 代理商： | MPC603E7TED |
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PID7t-603e Hardware Specifications
For More Information On This Product,
Go to: www.freescale.com
13
Electrical and Thermal Characteristics
1.4.3 JTAG AC Timing SpeciTcations
Table 10 provides the JTAG AC timing speciTcations as deTned in Figure 5, Figure 6, Figure 7 and
Figure 8.
Figure 5 provides the JTAG clock input timing diagram.
Figure 5. JTAG Clock Input Timing Diagram
Table 10. JTAG AC Timing Specifications
Vdd = AVdd = 2.5 ± 5% V dc, OVdd = 3.3 ± 5%, GND = 0 V dc, 0
￡
Tj
￡
105° C, C
L
= 50 pF
Num
Characteristic
Min
Max
Unit
Notes
TCK frequency of operation
0
16
MHz
1
TCK cycle time
62.5
—
ns
2
TCK clock pulse width measured at 1.4 V
25
—
ns
3
TCK rise and fall times
0
3
ns
4
TRST setup time to TCK rising edge
13
—
ns
1
5
TRST assert time
40
—
ns
6
Boundary scan input data setup time
6
—
ns
2
7
Boundary scan input data hold time
27
—
ns
2
8
TCK to output data valid
4
25
ns
3
9
TCK to output high impedance
3
24
ns
3
10
TMS, TDI data setup time
0
—
ns
11
TMS, TDI data hold time
25
—
ns
12
TCK to TDO data valid
4
24
ns
13
TCK to TDO high impedance
3
15
ns
Notes
:
1. TRST is an asynchronous signal. The setup time is for test purposes only.
2. Non-test signal input timing with respect to TCK.
3. Non-test signal output timing with respect to TCK.
TCK
2
2
1
VM
VM
VM
3
3
VM = Midpoint Voltage (1.4 V)
F
Freescale Semiconductor, Inc.
n
.
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