參數(shù)資料
型號: MPC603E7TED
廠商: Motorola, Inc.
英文描述: PowerPC 603e RISC Microprocessor
中文描述: RISC微處理器的PowerPC 603e
文件頁數(shù): 21/36頁
文件大?。?/td> 551K
代理商: MPC603E7TED
PID7t-603e Hardware Specifications
For More Information On This Product,
Go to: www.freescale.com
21
Package Descriptions
1.7.2.2 Mechanical Dimensions of the PBGA Package
Figure 11 shows the non-JEDEC package mechanical dimensions and
bottom surface nomenclature of the
the PBGA package.
Figure 11. Package Dimensions for the Plastic Ball Grid Array (PBGA)non-JEDEC Standard
Note that Table 11 lists the pinout to this non-JEDEC standard in order to be consistent with the CBGA
pinout.
T
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
256X
BOTTOM VIEW
E
0.20
6
5
4
3
2
1
b
0.30
0.15
C
D
D2
E2
A
B
C A B
SIDE VIEW
DIM
A
A1
A2
A3
b
D
D1
D2
E
E1
E2
e
MIN
2.10
0.50
1.10
0.50
0.60
23.00 BSC
19.05 REF
19.40
MAX
2.60
0.70
1.20
0.70
0.90
MILLIMETERS
23.00 BSC
19.05 REF
19.40
1.27 BSC
19.60
NOTES:
1.
DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
DIMENSIONS IN MILLIMETERS.
DIMENSION b IS MEASURED AT THE MAXIMUM
SOLDER BALL DIAMETER, PARALLEL TO
PRIMARY DATUM C.
PRIMARY DATUM C AND THE SEATING PLANE
ARE DEFINED BY THE SPHERICAL CROWNS OF
THE SOLDER BALLS.
2.
3.
4.
4X
7 8 9 101112131415
M
M
TOP VIEW
(D1)
15X
e
15X
e
(E1)
4X
e /2
0.20 C
0.35 C
A3
256X
C
A
A1
A2
PLANE
19.60
16
F
Freescale Semiconductor, Inc.
n
.
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