參數(shù)資料
型號: MPC603E7TED
廠商: Motorola, Inc.
英文描述: PowerPC 603e RISC Microprocessor
中文描述: RISC微處理器的PowerPC 603e
文件頁數(shù): 18/36頁
文件大小: 551K
代理商: MPC603E7TED
18
PID7t-603e Hardware Specifications
Package Descriptions
1.7 Package Descriptions
The following sections provide the CBGA and PBGA package parameters and the mechanical dimensions
for the 603e.
1.7.1 CBGA Package Description
The following sections provide the package parameters and mechanical dimensions for the CBGA package.
1.7.1.1 Package Parameters
The package parameters are as provided in the following list. The package type is 21 mm x 21 mm, 255-lead
ceramic ball grid array (CBGA).
Package outline
Interconnects
Pitch
Package height
21 mm x 21 mm
255
1.27 mm (50 mil)
Minimum: 2.45 mm
Maximum: 3.00 mm
0.89 mm (35 mil)
10 lbs
Ball diameter
Maximum heat sink force
TDI
A11
High
Input
TDO
A12
High
Output
TEA
H13
Low
Input
TLBISYNC
C04
Low
Input
TMS
B11
High
Input
TRST
C10
Low
Input
TS
J13
Low
I/O
TSIZ[0–2]
A13, D10, B12
High
Output
TT[0–4]
B13, A15, B16, C14, C15
High
I/O
WT
D02
Low
Output
VDD
2
F06, F08, F09, F11, G07, G10, H06, H08, H09, H11, J06, J08, J09, J11,
K07, K10, L06, L08, L09, L11
VOLTDETGND
3
F03
Low
Output
Notes:
1. These are test signals for factory use only and must be pulled up to OVdd for normal machine operation.
2. OVdd inputs supply power to the I/O drivers and Vdd inputs supply power to the processor core.
3. NC (no-connect) in the PID6-603e; internally tied to GND in the PID7v-603e and PID7t-603e CBGA and
PBGA package to indicate to the power supply that a low-voltage processor is present.
Table 11. Pinout Listing for the 255-Pin CBGA and PBGA Packages
Signal Name
Pin Number
Active
I/O
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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