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參數(shù)資料
| 型號： | MPC603E7TED |
| 廠商： | Motorola, Inc. |
| 英文描述： | PowerPC 603e RISC Microprocessor |
| 中文描述： | RISC微處理器的PowerPC 603e |
| 文件頁數(shù)： | 22/36頁 |
| 文件大?。?/td> | 551K |
| 代理商： | MPC603E7TED |
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22
PID7t-603e Hardware Specifications
Package Descriptions
Figure 12 shows the JEDEC package dimensions of the PBGA package.
Figure 12. Package Dimensions for the Plastic Ball Grid Array (PBGA)JEDEC Standard
Note that the pin numberings shown in Figure 12 do not match Table 11 and the pinout of the non-JEDEC
standard package (and the CBGA pinout) shown in Figure 11. Figure 11 should be used in conjunction with
Table 11 for the complete pinout description.
U
T
B
C
D
E
F
G
H
J
K
L
M
N
P
R
256X
BOTTOM VIEW
E
0.20
7
6
5
4
3
2
b
0.30
0.15
C
D
D2
E2
A
B
C A B
SIDE VIEW
DIM
A
A1
A2
A3
b
D
D1
D2
E
E1
E2
e
MIN
2.10
0.50
1.10
0.50
0.60
23.00 BSC
19.05 REF
19.40
MAX
2.60
0.70
1.20
0.70
0.90
MILLIMETERS
23.00 BSC
19.05 REF
19.40
1.27 BSC
19.60
NOTES:
1.
DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
DIMENSIONS IN MILLIMETERS.
DIMENSION b IS MEASURED AT THE MAXIMUM
SOLDER BALL DIAMETER, PARALLEL TO
PRIMARY DATUM C.
PRIMARY DATUM C AND THE SEATING PLANE
ARE DEFINED BY THE SPHERICAL CROWNS OF
THE SOLDER BALLS.
2.
3.
4.
4X
8 9 10111213141516
M
M
TOP VIEW
(D1)
15X
e
15X
e
(E1)
4X
e /2
0.20 C
0.35 C
A3
256X
C
A
A1
A2
SEATING
PLANE
19.60
17
CASE 1167-01
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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