MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
Index-13
Receiver
data register (RDRF) flag
15-57interrupt enable (RIE)
15-48Receiver Enable (RE)
15-46Reception of transmitted frames
16-14Register diagrams
registers
BBCMCR BBC module configuration register
4-19breakpoint address register (BAR)
23-53breakpoint counter A value and control register
breakpoint counter B value and control register
CALRAM_OTR CALRAM ownership trace
change of lock interrupt register (COLIR)
8-36comparator G-H value registers (CMPG–CMPH)
23-47condition register (CR)
3-16count register (CTR)
3-19CRAM_RBAx CALRAM region base address
CRAMMCR CALRAM module configuration
CRAMOVL CALRAM overlay configuration
DAE/source instruction service register (DSISR)
3-22data address register (DAR)
3-23DCCR0-DCCR15 decompressor class configuration
debug enable register (DER)
23-43decompressor class configuration
4-25decrementer register (DEC)
6-40development port data register (DER)
23-53documenter register (DEC)
3-23DPTRAM base address register (RAMBAR)
20-4DPTRAM module configuration register
DPTRAM test register (DPTTCR)
20-4dual-mapping base register (DMBR)
10-36dual-mapping option register (DMOR)
10-37EIBADR external interrupt relocation table base address
exception cause register (ECR)
23-41external master control register (EMCR)
6-29floating point (FPRs)
3-12floating point exception cause register (FPECR)
3-26floating point status and control register (FPSCR)
3-13general purpose registers (GPRs)
3-12hard reset configuration word register
I-bus support control register (COUNTA)
23-51I-bus support control register (ICTRL)
A-16implementation specific SPRs
3-25integer exception register (XER)
3-18internal memory map register (IMMR)
6-28interrupt in-service registers (SISR2 and SISR3)
6-37IRAMSTBY control register (VSRMCR)
8-37L2U global region attribute registers (L2U_GRA)
11-16L2U module configuration register (L2U_MCR)
11-13L2U region attribute registers (L2U_RAx)
11-15L2U region base address registers (L2U_RBAx)
11-14L-bus support control register 1 (LCTRL1)
23-47L-bus support control register 2 (LCTRL2)
23-48left justified, unsigned result format (LJURR)
13-33,
machine status save/restore register 0 (SRR0)
3-23machine status save/restore register 1 (SRR1)
3-23MBISM interrupt registers
17-69MBISM registers, list of
17-13MCPSMSCR MCPSM status/control register
17-18MDASM status/control register (duplicated)
MDASM status/control register (MDASMSCR)
17-44MDASMAR MDASM Data A register
17-41MDASMBR MDASM Data B register
17-42memory controller base registers (BR0-BR3)
10-32memory controller option registers (OR0-OR3)
10-34memory controller status registers (MSTAT) 10-32
MI_GRA global region atribute register
4-23MI_RA [0:3] region attribute register
4-22MI_RBA[0:3] region base address register
4-21MIOS14ER0 interrupt enable register
17-66MIOS14ER1 interrupt enable register
17-68MIOS14LVL0 interrupt level register 0
17-69MIOS14LVL1 interrupt level register 1
17-70MIOS14MCR module configuration register
17-15MIOS14RPR0 interrupt request pending register
MIOS14RPR1 interrupt request pending register