CDR3 Flash (UC3F) EEPROM
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
21-17
Table 21-6. RCW Bit Descriptions
Bits
Name
Description
0
EARB
arbitration. The default value is that internal arbitration hardware is used.
0 Internal arbitration is performed
1 External arbitration is assumed
1
IP
Initial interrupt prefix — This bit defines the initial value of the MSR[IP] immediately after reset. The
MSR[IP] bit defines the Interrupt Table location.
0 MSR[IP] = 0 after reset
1 MSR[IP] = 1 after reset
The default value is 0. See
Table 3-11 for more information.
2
BDRV
Bus pins drive strength — This bit determines the bus pins’ (address, data, and control) driving
capability to be either full or reduced drive. The bus default drive strength is full; upon default, it also
causes the CLKOUT drive strength to be full. See
Table 6-7 for more information. BDRV controls the
default state of COM[1] in the SIUMCR.
0 Full drive
1 Reduced drive
3
BDIS
Boot disable — If the BDIS bit is set, then memory controller is not activated after reset. If it is cleared
then the memory controller bank 0 is active immediately after reset such that it matches any addresses.
If a write to the OR0 register occurs after reset this bit definition is ignored. The default value is that the
0 Memory controller bank 0 is active and matches all addresses immediately after reset
1 Memory controller is not activated after reset.
4:5
BPS
Boot port size — This field defines the port size of the boot device on reset (BR0[PS]). If a write to the
OR0 register occurs after reset this field definition is ignored. See
Table 10-5 and
Table 10-8 for more
information.
00 32-bit port (default)
01 8-bit port
10 16-bit port
11 Reserved
6:8
—
Reserved. These bits must not be high in the reset configuration word.
9:10
DBGC[0:1]
this field definition. The default value is that these pins function as: VFLS[0:1], BI, BR, BG and BB. See
11
—
Reserved.
12
ATWC
Address type write enable configuration — The default value is that these pins function as WE pins.
0WE[0:3]/BE[0:3]/AT[0:3] functions as WE[0:3]/BE[0:3]
1WE[0:3]/BE[0:3]/AT[0:3] functions as AT[0:3]
13:14
EBDF
External bus division factor — This field defines the initial value of the external bus frequency. The
default value is that CLKOUT frequency is equal to that of the internal clock (no division). See
Table 8-9.15
IWS
Interlock write select — This bit determines which interlock write operation should be used during the
clear censorship operation.
IWS always comes from the UC3FCFIG, it will never use the external reset configuration word
(RSTCONF=0) or the default internal reset configuration word (RSTCONF=1 and HC=1).
0 Interlock write is a write to any UC3F array location
1 Interlock write is a write to the UC3FMCR register.