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參數(shù)資料
| 型號(hào)： | ML53812-2 |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP176 |
| 封裝： | LQFP-176 |
| 文件頁數(shù)： | 8/64頁 |
| 文件大小： | 668K |
| 代理商： | ML53812-2 |
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s ML53812-2 s ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
12
Oki Semiconductor
The interrupts are both globally and individually maskable, and are signaled to the processor via the INT
pin (pin 10). The INT pin can be configured to operate as either push-pull or open drain, and its polarity
(active high or active low) is also selectable.
All of these interrupt latches have an individual enable/clear register and an individual interrupt mask
register associated with them.
5.17 GPIO Ports
Four general purpose input/output ports are provided. The ports may be individually configured to a
variety of modes and can also be used as interrupt sources. Possible uses of the GPIO ports would be con-
trolling H.100/H.110 termination switches or implementing the SCbus CLKFAIL signal.
5.18 Message Channel
The ML53812-2 provides a complete interface between the CT_MC CT Bus signal and a local HDLC con-
troller. This includes generation of MC_CLK as well as buffering of MC_TXD and MC_RXD.
Figure 4. CT_C8_A and CT_C8_B Error Detection
CT_C8_(A/B)
Expected Delay (Approx. 125 ns)
Late Allowance (35 ns)
Rising edge of CT_C8 occurring
after this limit will trigger an
interrupt (if enabled).
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