
––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– s ML53812-2 s
7
Oki Semiconductor
5.0 FUNCTIONAL DESCRIPTION
The ML53812-2 has the following interfaces:
5.1 Local Bus
The local bus consists of up to eight serial input ports and eight serial output ports, totalling 512 possible
local bus connections to the CT Bus. The input and output ports can be configured independently as two
groups of four 2 Mb/s streams, two 4 Mb/s streams, or one 8 Mb/s stream. The chip includes two inde-
pendent, configurable local clock and frame synchronization signals. The local clocks have configurable
polarity and frequency that can be set to 2 MHz, 4 MHz, 8 MHz, or 16 MHz regardless of local stream
data rate. The local frame syncs also have a configurable polarity and can be set to use one of three fram-
ing formats (early, straddle, or late).
To transfer data to and from the local bus, the ML53812-2 allows the user to select a minimum delay or
constant delay buffer mode on a per channel basis. In the minimum delay mode, the input-output buffer
transfer occurs on the next 2 Mb/s time slot boundary, reducing any potential channel delay for classic
voice processing applications. In the constant delay mode, the buffer transfer occurs at the frame bound-
ary for bundling and proper switching of wide-band data, for data sent on the ISDN H channel.
Microprocessor Interface
Local Serial Data In
Local Serial Data Out
Local Timing
Analog PLL Reference Clock
CT Bus Timing
CT Bus Serial Data
Figure 2. Block Diagram
8 Channel
Stream Switch
256 x 4096
Transmit Switch
Master
Digital PLL
4352 x 256
Receive Switch
Slave Digital
PLL
Configuration &
Routing Register
Analog
PLL
Local
Connect
CT Bus Serial Data
CT Bus Timing
131.072 MHz
Internal Timing
Internal Control
Microprocessor
Interface
APLL
Reference Clock
Local Timing
Local Serial
Data Out
Local Serial
Data In