參數(shù)資料
型號(hào)： ML53812-2
廠商： OKI ELECTRIC INDUSTRY CO LTD
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQFP176
封裝： LQFP-176
文件頁(yè)數(shù)： 42/64頁(yè)
文件大小： 668K
代理商： ML53812-2
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43
Oki Semiconductor
6.9 Receive Switch Routing Registers, AR = 30ffh:3000h (Ch. 255:0)
Note: To ensure compatibility with subsequent versions of this device, write “0” to all "Reserved" bits in the
routing registers. All "Reserved" routing registers read-back "0".
Note: Internally all time-slots run at 8Mb/s. To receive from CT_D streams running at a slower rate, use the
following conversion:
If CT_D stream is operating at 4Mb/s, receive switch input time-slot register = CT_D time-slot X 2 + 1.
If CT_D stream is operating at 2Mb/s, receive switch input time-slot register = CT_D time-slot X 4 + 3.
DR_0
Definition
[6:0]
Input Time-slot
7
Reserved (write zero)
Input Time-slot [6:0] (Read/Write)
Selects the CT_D time-slot for receive channel routing.
00h
→
Time-slot 0 (Default)
01h
→
Time-slot 1
02h
→
Time-slot 2
7eh
→
Time-slot 126
7fh
→
Time-slot 127
DR_1
Definition
[4:0]
Input Data Stream
[6:5]
Reserved (write zero)
7
Output Enable
Input Data Stream [4:0] (Read/Write)
Selects the CT_D data stream for receive channel routing.
00h
→
CT_D_[0] (Default)
01h
→
CT_D_[1]
02h
→
CT_D_[2]
1eh
→
CT_D_[30]
1fh
→
CT_D_[31]
Output Enable (Read/Write)
Controls the Output Enable for the channel’s local stream.
0
→
Output Disabled (Default)
1
→
Output Enabled
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