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參數(shù)資料
| 型號(hào)： | ML53812-2 |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP176 |
| 封裝： | LQFP-176 |
| 文件頁數(shù)： | 6/64頁 |
| 文件大?。?/td> | 668K |
| 代理商： | ML53812-2 |
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s ML53812-2 s ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
10
Oki Semiconductor
To make an MTIE compliant reference switch, enable "Condition Master PLL reference", select the "Mas-
ter PLL Reference", and configure the "Master PLL Mode " to normal.The master PLL will be locked to
the selected reference.
The following sequence will produce an MTIE-compliant reference switch:
1. Change the "Master PLL Mode" from Normal to Holdover. The master PLL can also be configured to
make this change automatically in the event of a master PLL error.
2. Change the "Master PLL Reference Select" to the new reference, or change the reference source of
CT_NETREF.
3. Change the "Master PLL Mode" back to Normal.
5.10 Reference Master
CT_NETREF_1 and CT_NETREF_2 can be independently configured to output a reference signal to the
CT Bus selected from one of eight local network reference inputs. The local network references can be
passed through or divided by 192, 193, or 256.
5.11 Local Clock and Frame Sync
Two sets of local clock and frame sync are provided. A variety of clock frequencies, polarities, and fram-
ing formats may be selected to allow "glue less" local port interfacing. Each set of local clock and frame
sync may be configured separately. The frequency selection is independent of the local stream rate.
5.12 Local Streams
The local streams consist of up to eight serial input ports and eight serial output ports, defined as two
groups of 128 time-slots. Each group can be independently configured to operate as four 2 Mb/s streams,
two 4 Mb/s streams, or one 8 Mb/s stream.
MTIE Specifications
ML53812-2
62411 Stratum 3 and 4E
MTIE during rearrangement
100 ns
1 s
Phase change slope
81 ns / 1.326 ms
Local Stream Time Slot to Channel Mapping
Local stream
8Mb/s stream rate time slot 127:0
4Mb/s stream rate time slot 63:0
2Mb/s stream rate time slot 31:0
L_SI_0,L_SO_0
channel 127:0
channel 63:0
channel 31:0
L_SI_1,L_SO_1
-
channel 127:64
channel 63:32
L_SI_2,L_SO_2
-
channel 95:64
L_SI_3,L_SO_3
-
channel 127:96
L_SI_4,L_SO_4
channel 255:128
channel 191:128
channel 159:128
L_SI_5,L_SO_5
-
channel 255:192
channel 191:160
L_SI_6,L_SO_6
-
channel 223:192
L_SI_7,L_SO_7
-
channel 255:224
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