參數(shù)資料
型號: MFRC53001T
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡
英文描述: ISO-IEC 14443 A Reader IC
封裝: MFRC53001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 5, 2005,;MFRC53001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1
文件頁數(shù): 96/115頁
文件大?。?/td> 2590K
代理商: MFRC53001T
MFRC530_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 6 July 2010
057433
96 of 115
NXP Semiconductors
MFRC530
ISO/IEC 14443 A Reader IC
The clock applied to the MFRC530 acts as a time constant for the synchronous system’s
encoder and decoder. The stability of the clock frequency is an important factor for
ensuring proper performance. To obtain highest performance, clock jitter must be as small
as possible. This is best achieved using the internal oscillator buffer and the
recommended circuitry; see
Section 9.8 on page 27
.
14. EEPROM characteristics
The EEPROM size is 32
×
16
×
8 = 4096 bit.
Table 166. EEPROM characteristics
Symbol
Parameter
N
endu(W_ER)
write or erase endurance
t
ret
retention time
t
er
erase time
t
a(W)
write access time
15. Application information
15.1 Typical application
15.1.1
Circuit diagram
Figure 24
shows a typical application where the antenna is directly matched to the
MFRC530
Conditions
erase/write cycles
T
amb
55
°
C
Min
100000
10
-
-
Typ
-
-
-
-
Max
-
-
2.9
2.9
Unit
Hz
year
ms
ms
Fig 24. Application example circuit diagram: directly matched antenna
001aak625
DVDD
RSTPD
AVDD
TVDD
DVDD
Reset
AVDD
TVDD
DVSS
control lines
data bus
IRQ
OSCIN
OSCOUT
13.56 MHz
AVSS
VMID
RX
TX2
TVSS
TX1
IRQ
15 pF
15 pF
C0
C0
C2a
C2b
C3
R2
R1
L0
L0
C1
C1
C4
100 nF
MICROPROCESSOR
BUS
MICROPROCESSOR
DEVICE
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