參數(shù)資料
型號： MFRC53001T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網(wǎng)絡(luò)
英文描述： ISO-IEC 14443 A Reader IC
封裝： MFRC53001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 5, 2005,;MFRC53001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1
文件頁數(shù)： 77/115頁
文件大小： 2590K
代理商： MFRC53001T
MFRC530_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 6 July 2010
057433
77 of 115
NXP Semiconductors
MFRC530
ISO/IEC 14443 A Reader IC
Figure 17
also shows write access to the FIFOData register just before the FIFO buffer’s
status is checked. This leads to FIFO empty state being held LOW which keeps the
accept further data active. The new byte written to the FIFO buffer is transmitted using the
RF interface.
Accept further data is only changed by the check FIFO empty function. This function
verifies FIFO empty for one bit duration before the last expected bit transmission.
Table 136. Transmission of frames of more than 64 bytes
Frame definition
8-bit with parity
8-bit without parity
x-bit without parity
11.2.2
Receive command 16h
Table 137. Receive command 16h
Command
The Receive command activates the receiver circuitry. All data received from the RF
interface is written to the FIFO buffer. The Receive command can be started either using
the microprocessor or automatically during execution of the Transceive command.
Remark:
This command can only be used for test purposes since there is no timing
relationship to the Transmit command.
11.2.2.1
Using the Receive command
After starting the Receive command, the internal state machine decrements to the RxWait
register value on every bit-clock. The analog receiver circuitry is prepared and activated
from 3 down to 1. When the counter reaches 0, the receiver starts monitoring the incoming
signal at the RF interface.
When the signal strength reaches a level higher than the RxThreshold register
MinLevel[3:0] bits value, it starts decoding. The decoder stops when the signal can longer
be detected on the receiver input pin RX. The decoder sets bit RxIRq indicating receive
termination.
The different phases of the receive sequence are monitored using the PrimaryStatus
register ModemState[2:0] bits; see
Section 11.2.4 on page 80
.
Remark:
Since the counter values from 3 to 0 are needed to initialize the analog receiver
circuitry, the minimum value for RxWait[7:0] is 3.
Verification at:
8
th
bit
7
th
bit
(x
1)
th
bit
Value
Action
Arguments
and data
-
Returned
data
data stream
Receive
16h
activates receiver circuitry
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