參數(shù)資料
型號: MFRC53001T
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡(luò)
英文描述: ISO-IEC 14443 A Reader IC
封裝: MFRC53001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 5, 2005,;MFRC53001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1
文件頁數(shù): 64/115頁
文件大?。?/td> 2590K
代理商: MFRC53001T
MFRC530_33
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NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 6 July 2010
057433
64 of 115
NXP Semiconductors
MFRC530
ISO/IEC 14443 A Reader IC
[1]
With ISO/IEC 14443 A, this bit must be set to logic 0.
[2]
With ISO/IEC 14443 A, this bit must be set to logic 1.
10.5.5.4
CRCPresetLSB register
LSB of the preset value for the CRC register.
Table 101. CRCPresetLSB register (address: 23h) reset value: 0101 0011b, 63h bit allocation
Bit
7
6
5
4
Symbol
CRCPresetLSB[7:0]
Access
Table 102. CRCPresetLSB register bit descriptions
Bit
Symbol
7 to 0
CRCPresetLSB[7:0]
10.5.5.5
CRCPresetMSB register
MSB of the preset value for the CRC register.
Table 103. CRCPresetMSB register (address: 24h) reset value: 0101 0011b, 63h bit
allocation
Bit
7
6
5
Symbol
Access
Table 104. CRCPresetMSB bit descriptions
Bit
Symbol
7 to 0 CRCPresetMSB[7:0]
10.5.5.6
PreSet25 register
These values must not be changed.
Table 105. PreSet25 register (address: 25h) reset value: 0000 0000b, 00h bit allocation
Bit
7
6
5
Symbol
Access
1
ParityOdd
1
0
1
odd parity is generated or expected
[2]
even parity is generated or expected
a parity bit is inserted in the transmitted data stream after each byte
and expected in the received data stream after each byte (MIFARE,
ISO/IEC 14443 A)
no parity bit is inserted or expected
0
ParityEn
0
Table 100. ChannelRedundancy bit descriptions
…continued
Bit
Symbol
Value
Function
3
2
1
0
R/W
Description
defines the start value for CRC calculation. This value is loaded
into the CRC at the beginning of transmission, reception and
the CalcCRC command (if CRC calculation is enabled).
4
3
2
1
0
CRCPresetMSB[7:0]
R/W
Description
defines the starting value for CRC calculation. This value is
loaded into the CRC at the beginning of transmission, reception
and the CalcCRC command (if the CRC calculation is enabled)
Remark:
This register is not relevant if CRC8 is set to logic 1.
4
3
2
1
0
00000000
R/W
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