參數(shù)資料
型號(hào): MFRC53001T
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡(luò)
英文描述: ISO-IEC 14443 A Reader IC
封裝: MFRC53001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 5, 2005,;MFRC53001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1
文件頁數(shù): 112/115頁
文件大小: 2590K
代理商: MFRC53001T
MFRC530_33
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NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 6 July 2010
057433
112 of 115
NXP Semiconductors
MFRC530
ISO/IEC 14443 A Reader IC
23. Figures
Fig 1.
Fig 2.
Fig 3.
MFRC530 block diagram. . . . . . . . . . . . . . . . . . . .4
MFRC530 pin configuration. . . . . . . . . . . . . . . . . .5
Connection to microprocessor: separate read
and write strobes . . . . . . . . . . . . . . . . . . . . . . . . . .8
Connection to microprocessor: common read
and write strobes . . . . . . . . . . . . . . . . . . . . . . . . . .9
Connection to microprocessor: EPP common
read/write strobes and handshake. . . . . . . . . . . . .9
Connection to microprocessor: SPI . . . . . . . . . . .10
Key storage format . . . . . . . . . . . . . . . . . . . . . . .16
Timer module block diagram . . . . . . . . . . . . . . . .22
The StartUp procedure. . . . . . . . . . . . . . . . . . . . .26
Fig 10. Quartz clock connection . . . . . . . . . . . . . . . . . . .27
Fig 11. Receiver circuit block diagram. . . . . . . . . . . . . . .31
Fig 12. Automatic Q-clock calibration . . . . . . . . . . . . . . .32
Fig 13. Serial signal switch block diagram. . . . . . . . . . . .35
Fig 14. Crypto1 key handling block diagram . . . . . . . . . .38
Fig 15. Transmitting bit oriented frames . . . . . . . . . . . . .75
Fig 16. Timing for transmitting byte oriented frames . . . .76
Fig 17. Timing for transmitting bit oriented frames. . . . . .76
Fig 18. Card communication state diagram. . . . . . . . . . .81
Fig 19. EEPROM programming timing diagram. . . . . . . .83
Fig 20. Separate read/write strobe timing diagram . . . . .92
Fig 21. Common read/write strobe timing diagram . . . . .93
Fig 22. Timing diagram for common read/write strobe;
EPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Fig 23. Timing diagram for SPI . . . . . . . . . . . . . . . . . . . .95
Fig 24. Application example circuit diagram: directly
matched antenna. . . . . . . . . . . . . . . . . . . . . . . . .96
Fig 25. TX control signals . . . . . . . . . . . . . . . . . . . . . . .100
Fig 26. RX control signals . . . . . . . . . . . . . . . . . . . . . . .101
Fig 27. ISO/IEC 14443 A receiving path Q-clock. . . . . .103
Fig 28. Package outline SOT287-1 . . . . . . . . . . . . . . . .104
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
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