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參數資料
| 型號： | MFRC53001T |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通信及網絡 |
| 英文描述： | ISO-IEC 14443 A Reader IC |
| 封裝： | MFRC53001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 5, 2005,;MFRC53001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1 |
| 文件頁數： | 32/115頁 |
| 文件大?。?/td> | 2590K |
| 代理商： | MFRC53001T |
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MFRC530_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 6 July 2010
057433
32 of 115
NXP Semiconductors
MFRC530
ISO/IEC 14443 A Reader IC
9.10.2.1
Automatic Q-clock calibration
The quadrature demodulation concept of the receiver generates a phase signal (I-clock)
and a 90
°
phase-shifted quadrature signal (Q-clock). To achieve the optimum
demodulator performance, the Q-clock and the I-clock must be phase-shifted by 90
°
. After
the reset phase, a calibration procedure is automatically performed.
Automatic calibration can be set-up to execute at the end of each Transceive command if
bit ClkQCalib = logic 0. Setting bit ClkQCalib = logic 1 disables all automatic calibrations
except after the reset sequence. Automatic calibration can also be triggered by the
software when bit ClkQCalib has a logic 0 to logic 1 transition.
Remark:
The duration of the automatic Q-clock calibration is 65 oscillator periods or
approximately 4.8
μ
s.
The ClockQControl register’s ClkQDelay[4:0] value is proportional to the phase-shift
between the Q-clock and the I-clock. The ClkQ180Deg status flag bit is set when the
phase-shift between the Q-clock and the I-clock is greater than 180
°
.
Remark:
The StartUp configuration file enables automatic Q-clock calibration after a reset
If bit ClkQCalib = logic 1, automatic calibration is not performed. Leaving this bit set to
logic 1 can be used to permanently disable automatic calibration.
It is possible to write data to the ClkQDelay[4:0] bits using the microprocessor. The
aim could be to disable automatic calibration and set the delay using the software.
Configuring the delay value using the software requires bit ClkQCalib to have been
previously set to logic 1 and a time interval of at least 4.8
μ
s has elapsed. Each delay
value must be written with bit ClkQCalib set to logic 1. If bit ClkQCalib is logic 0, the
configured delay value is overwritten by the next automatic calibration interval.
Fig 12. Automatic Q-clock calibration
001aak616
calibration impulse
from reset sequence
a rising edge initiates
Q-clock calibration
ClkQCalib bit
calibration impulse
from end of
Transceive command
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MFRC53001T/0FE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:ISO/IEC 14443 A Reader IC |
| MFRC53001T/0FE,112 | 功能描述:RFID應答器 MIFARE HS READER RoHS:否 制造商:Murata 存儲容量:512 bit 工作溫度范圍:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| MFRC53001T/0FE,518 | 功能描述:RFID應答器 IC READER 13.56MHZ RoHS:否 制造商:Murata 存儲容量:512 bit 工作溫度范圍:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| MFRC53001T/0FE112 | 制造商:NXP Semiconductors 功能描述:CNTCLESS RC 3.3V ISO14443-A/B |
| MFRC531 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Short Form Specification |
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