參數(shù)資料
型號： MFRC53001T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網(wǎng)絡(luò)
英文描述： ISO-IEC 14443 A Reader IC
封裝： MFRC53001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 5, 2005,;MFRC53001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1
文件頁數(shù)： 25/115頁
文件大小： 2590K
代理商： MFRC53001T
MFRC530_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 6 July 2010
057433
25 of 115
NXP Semiconductors
MFRC530
ISO/IEC 14443 A Reader IC
9.6 Power reduction modes
9.6.1
Hard power-down
Hard power-down is enabled when pin RSTPD is HIGH. This turns off all internal current
sinks including the oscillator. All digital input buffers are separated from the input pads and
defined internally (except pin RSTPD itself). The output pins are frozen at a given value.
The status of all pins during a hard power-down is shown in
Table 24
.
Table 24.
Symbol
OSCIN
IRQ
MFIN
MFOUT
TX1
9.6.2
Soft power-down mode
Soft power-down mode is entered immediately using the Control register bit PowerDown.
All internal current sinks, including the oscillator buffer, are switched off. The digital input
buffers are not separated from the input pads and keep their functionality. In addition, the
digital output pins do not change their state.
After resetting the Control register bit PowerDown, the bit indicating Soft power-down
mode is only cleared after 512 clock cycles. Resetting it does not immediately clear it. The
PowerDown bit is automatically cleared when the Soft power-down mode is exited.
Remark:
When the internal oscillator is used, time (t
osc
) is required for the oscillator to
become stable. This is because the internal oscillator is supplied by V
DDA
and any clock
cycles will not be detected by the internal logic until V
DDA
is stable.
Signal on pins during Hard power-down
Pin
1
2
3
4
5
Type
I
O
I
O
O
Description
not separated from input, pulled to AVSS
high-impedance
separated from input
LOW
HIGH, if bit TX1RFEn = logic 1
LOW, if bit TX1RFEn = logic 0
HIGH, only if bit TX2RFEn = logic 1 and bit
TX2Inv = logic 0
otherwise LOW
separated from input
separated from input
separated from input
separated from input
separated from input
separated from input
separated from input
separated from input
high-impedance
not changed
pulled to V
DDA
not changed
HIGH
TX2
7
O
NCS
NWR
NRD
D0 to D7
ALE
A0
A1
A2
AUX
RX
VMID
RSTPD
OSCOUT
9
10
11
13 to 20
21
22
23
24
27
29
30
31
32
I
I
I
I/O
I
I/O
I
I
O
I
A
I
O
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