參數(shù)資料
型號(hào)： MFRC50001T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Highly integrated ISO-IEC 14443 A reader IC
封裝： MFRC50001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 15, 2005,;
文件頁(yè)數(shù)： 97/110頁(yè)
文件大?。?/td> 841K
代理商： MFRC50001T
MFRC500_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
97 of 110
NXP Semiconductors
MFRC500
Highly Integrated ISO/IEC 14443 A Reader IC
15.2.3
Digital test signals
Digital test signals can be routed to pin MFOUT by setting bit SignalToMFOUT = logic 1. A
digital test signal is selected using the TestDigiSelect register TestDigiSignalSel[6:0] bits.
The signals selected by the TestDigiSignalSel[6:0] bits are shown in
Table 162
.
Table 162. Digital test signal selection
TestDigiSignalSel
[6:0]
F4h
E4h
If test signals are not used, the TestDigiSelect register address value must be 00h.
Remark:
All other values for TestDigiSignalSel[6:0] are for production test purposes only.
15.2.4
Analog and digital test signal Examples
Figure 25
shows a MIFARE card’s answer to a request command using the Q-clock
receiving path. RX reference is given to show the Manchester modulated signal on pin
RX.
The signal is demodulated and amplified in the receiver circuitry. Signal VRXAmpQ is the
amplified side-band signal using the Q-clock for demodulation. The signals VCorrDQ and
VCorrNQ were generated in the correlation circuitry. They are processed further in the
evaluation and digitizer circuitry.
Signals VEvalR and VEvalL show the evaluation of the signal’s right and left half-bit.
Finally, the digital test signal s_data shows the received data. This is then sent to the
internal digital circuit and s_valid which indicates the received data stream is valid.
B
C
D
E
F
VEvalR
VTemp
reserved
reserved
reserved
evaluation signal from the right half-bit
temperature voltage derived from band gap
reserved for future use
reserved for future use
reserved for future use
Table 161. Analog test signal selection
…continued
Value
Signal Name
Description
Signal name
Description
s_data
s_valid
data received from the card
when logic 1 is returned the s_data and s_coll signals are
valid
when logic 1 is returned a collision has been detected in the
current bit
internal serial clock:
during transmission, this is the encoder clock
during reception this is the receiver clock
internal synchronized read signal which is derived from the
parallel microprocessor interface
internal synchronized write signal which is derived from the
parallel microprocessor interface
internal 13.56 MHz clock
output as defined by the MFOUTSelect register
MFOUTSelect[2:0] bits routed to pin MFOUT
D4h
s_coll
C4h
s_clock
B5h
rd_sync
A5h
wr_sync
96h
00h
int_clock
no test signal
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