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| 型號： | MFRC50001T |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Highly integrated ISO-IEC 14443 A reader IC |
| 封裝： | MFRC50001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 15, 2005,; |
| 文件頁數(shù)： | 78/110頁 |
| 文件大小： | 841K |
| 代理商： | MFRC50001T |
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MFRC500_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
78 of 110
NXP Semiconductors
MFRC500
Highly Integrated ISO/IEC 14443 A Reader IC
11.3.1.2
Timing diagram
Figure 18
shows programming five bytes into the EEPROM.
Assuming that the MFRC500 finds and reads byte 0 before the microprocessor is able to
write byte 1 (t
prog,del
= 300 ns). This causes the MFRC500 to start the programming cycle
(t
prog
), which takes approximately 5.8 ms to complete. In the meantime, the
microprocessor stores byte 1 to byte 4 in the FIFO buffer.
If the EEPROM start byte address is 16Ch then byte 0 is stored at that address. The
MFRC500 copies the subsequent data bytes into the EEPROM input buffer. Whilst
copying byte 3, it detects that this data byte has to be programmed at the EEPROM byte
address 16Fh. As this is the end of the memory block, the MFRC500 automatically starts
a programming cycle.
Next, byte 4 is programmed at the EEPROM byte address 170h. As this is the last data
byte, the E2Ready and TxIRq flags are set indicating the end of the EEPROM
programming activity.
Although all data has been programmed into the EEPROM, the MFRC500 stays in the
WriteE2 command. Writing more data to the FIFO buffer would lead to another EEPROM
programming cycle continuing from EEPROM byte address 171h. The command is
stopped using the Idle command.
11.3.1.3
WriteE2 command error flags
Programming is restricted for EEPROM block 0 (EEPROM byte address 00h to 0Fh). If
you program these addresses, the AccessErr flag is set and a programming cycle is not
started.
Addresses above 1FFh are taken modulo 200h; see
Section 9.2 on page 10
for the
EEPROM memory organization.
Fig 18. EEPROM programming timing diagram
001aak623
NWR
data
WriteE2
command active
EEPROM
programming
E2Ready
TxIRq
write
E2
addr
LSB
addr
MSB
byte 0
byte 1
t
prog,del
byte 2
byte 3
byte 4
programming byte 0
t
prog
programming
byte 1, byte 2 and byte 3
t
prog
programming byte 4
t
prog
Idle
command
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