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參數(shù)資料
| 型號： | MFRC50001T |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Highly integrated ISO-IEC 14443 A reader IC |
| 封裝： | MFRC50001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 15, 2005,; |
| 文件頁數(shù)： | 73/110頁 |
| 文件大小： | 841K |
| 代理商： | MFRC50001T |
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MFRC500_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
73 of 110
NXP Semiconductors
MFRC500
Highly Integrated ISO/IEC 14443 A Reader IC
11.2.2.2
RF channel redundancy and framing
The decoder expects the SOF pattern at the beginning of each data stream. When the
SOF is detected, it activates the serial-to-parallel converter and gathers the incoming data
bits. Every completed byte is forwarded to the FIFO buffer.
If an EOF pattern is detected or the signal strength falls below the RxThreshold register
MinLevel[3:0] bits setting, both the receiver and the decoder stop. Then the Idle command
is entered and an appropriate response for the microprocessor is generated (interrupt
request activated, status flags set).
When the ChannelRedundancy register bit RxCRCEn is set, a CRC block is expected.
The CRC block can be one byte or two bytes depending on the ChannelRedundancy
register CRC8 bit setting.
Remark:
If the CRC block received is correct, it is not sent to the FIFO buffer. This is
realized by shifting the incoming data bytes through an internal buffer of either one or two
bytes (depending on the defined CRC). The CRC block remains in this internal buffer.
Consequently, all data bytes in the FIFO buffer are delayed by one or two bytes. If the
CRC fails, all received bytes are sent to the FIFO buffer including the faulty CRC.
If ParityEn is set in the ChannelRedundancy register, a parity bit is expected after each
byte. If ParityOdd = logic 1, the expected parity is odd, otherwise even parity is expected.
11.2.2.3
Collision detection
If more than one card is within the RF field during the card selection phase, they both
respond simultaneously. The MFRC500 supports the algorithm defined in
ISO/IEC 14443 A to resolve card serial number data collisions by performing the
anti-collision procedure. The basis for this procedure is the ability to detect bit-collisions.
Bit-collision detection is supported by the Manchester coding bit encoding scheme used in
the MFRC500. If in the first and second half-bit of a subcarrier, modulation is detected,
instead of forwarding a 1-bit or 0-bit, a bit-collision is indicated. The MFRC500 uses the
RxThreshold register CollLevel[3:0] bits setting to distinguish between a 1-bit or 0-bit and
a bit-collision. If the amplitude of the half-bit with smaller amplitude is larger than that
defined by the CollLevel[3:0] bits, the MFRC500 flags a bit-collision using the error flag
CollErr. If a bit-collision is detected in a parity bit, the ParityErr flag is set.
On a detected collision, the receiver continues receiving the incoming data stream. In the
case of a bit-collision, the decoder sends logic 1 at the collision position.
Remark:
As an exception, if bit ZeroAfterColl is set, all bits received after the first
bit-collision are forced to zero, regardless whether a bit-collision or an unequivocal state
has been detected. This feature makes it easier for the control software to perform the
anti-collision procedure as defined in ISO/IEC 14443 A.
When the first bit collision in a frame is detected, the bit-collision position is stored in the
CollPos register.
Table 132
shows the collision positions.
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