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參數(shù)資料
| 型號： | MFRC50001T |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Highly integrated ISO-IEC 14443 A reader IC |
| 封裝： | MFRC50001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 15, 2005,; |
| 文件頁數(shù)： | 15/110頁 |
| 文件大?。?/td> | 841K |
| 代理商： | MFRC50001T |
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MFRC500_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
15 of 110
NXP Semiconductors
MFRC500
Highly Integrated ISO/IEC 14443 A Reader IC
When the microprocessor starts a command, the MFRC500 can still access the FIFO
buffer while the command is running. Only one FIFO buffer has been implemented which
is used for input and output. Therefore, the microprocessor must ensure that there are no
inadvertent FIFO buffer accesses.
Table 13
gives an overview of FIFO buffer access
during command processing.
Table 13.
Active
command
9.3.2
Controlling the FIFO buffer
In addition to writing to and reading from the FIFO buffer, the FIFO buffer pointers can be
reset using the FlushFIFO bit. This changes the FIFOLength[6:0] value to zero, bit
FIFOOvfl is cleared and the stored bytes are no longer accessible. This enables the FIFO
buffer to be written with another 64 bytes of data.
9.3.3
FIFO buffer status information
The microprocessor can get the following FIFO buffer status data:
the number of bytes stored in the FIFO buffer: bits FIFOLength[6:0]
the FIFO buffer full warning: bit HiAlert
the FIFO buffer empty warning: bit LoAlert
the FIFO buffer overflow warning: bit FIFOOvfl.
Remark:
Setting the FlushFIFO bit clears the FIFOOvfl bit.
The MFRC500 can generate an interrupt signal when:
bit LoAlertIRq is set to logic 1 and bit LoAlert = logic 1, pin IRQ is activated.
bit HiAlertIRq is set to logic 1 and bit HiAlert = logic 1, pin IRQ activated.
The HiAlert flag bit is set to logic 1 only when the WaterLevel[5:0] bits or less can be
stored in the FIFO buffer. The trigger is generated by
Equation 1
:
FIFO buffer access
FIFO buffer
μ
p Write
-
-
yes
-
yes
Remark
μ
p Read
-
-
-
yes
yes
StartUp
Idle
Transmit
Receive
Transceive
the microprocessor has to know the state of the
command (transmitting or receiving)
WriteE2
ReadE2
yes
yes
-
yes
the microprocessor has to prepare the arguments,
afterwards only reading is allowed
LoadKeyE2
LoadKey
Authent1
Authent2
LoadConfig
CalcCRC
yes
yes
yes
-
yes
yes
-
-
-
-
-
-
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