參數(shù)資料
型號(hào)： MFRC50001T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Highly integrated ISO-IEC 14443 A reader IC
封裝： MFRC50001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 15, 2005,;
文件頁(yè)數(shù)： 59/110頁(yè)
文件大?。?/td> 841K
代理商： MFRC50001T
MFRC500_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
59 of 110
NXP Semiconductors
MFRC500
Highly Integrated ISO/IEC 14443 A Reader IC
[1]
With ISO/IEC 14443 A, this bit must be set to logic 1.
10.5.5.4
CRCPresetLSB register
LSB of the preset value for the CRC register.
Table 95.
Bit
Symbol
Access
Table 96.
Bit
7 to 0
10.5.5.5
CRCPresetMSB register
MSB of the preset value for the CRC register.
Table 97.
Table 98.
Bit
7 to 0 CRCPresetMSB[7:0]
10.5.5.6
PreSet25 register
These values must not be changed.
Table 99.
Bit
Symbol
Access
1
ParityOdd
1
0
1
odd parity is generated or expected
[1]
even parity is generated or expected
a parity bit is inserted in the transmitted data stream after each byte
and expected in the received data stream after each byte (MIFARE,
ISO/IEC 14443 A)
no parity bit is inserted or expected
0
ParityEn
0
Table 94.
Bit
ChannelRedundancy bit descriptions
…continued
Symbol
Value
Function
CRCPresetLSB register (address: 23h) reset value: 0101 0011b, 63h bit allocation
7
6
5
4
CRCPresetLSB[7:0]
R/W
3
2
1
0
CRCPresetLSB register bit descriptions
Symbol
CRCPresetLSB[7:0]
Description
defines the start value for CRC calculation. This value is loaded
into the CRC at the beginning of transmission, reception and
the CalcCRC command (if CRC calculation is enabled).
CRCPresetMSB register (address: 24h) reset value: 0101 0011b, 63h bit
allocation
7
6
5
4
CRCPresetMSB[7:0]
Bit
Symbol
Access
3
2
1
0
R/W
CRCPresetMSB bit descriptions
Symbol
Description
defines the starting value for CRC calculation. This value is
loaded into the CRC at the beginning of transmission, reception
and the CalcCRC command (if the CRC calculation is enabled)
Remark:
This register is not relevant if CRC8 is set to logic 1.
PreSet25 register (address: 25h) reset value: 0000 0000b, 00h bit allocation
7
6
5
4
3
2
1
0
00000000
R/W
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